K4S561632D-TC/L1H データシートの表示（PDF） - Samsung

部品番号

コンポーネント説明

メーカー

K4S561632D-TC/L1H

256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL

Samsung 

K4S561632D

4M x 16Bit x 4 Banks Synchronous DRAM

CMOS SDRAM

FEATURES

• JEDEC standard 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

-. CAS latency (2 & 3)

-. Burst length (1, 2, 4, 8 & Full page)

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system

clock.

• Burst read single-bit write operation

• DQM for masking

• Auto & self refresh

• 64ms refresh period (8K Cycle)

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The K4S561632D is 268,435,456 bits synchronous high data rate

Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabri-

cated with SAMSUNG's high performance CMOS technology. Syn-

chronous design allows precise cycle control with the use of

system clock I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable burst length and

programmable latencies allow the same device to be useful for a

variety of high bandwidth, high performance memory system appli-

cations.

ORDERING INFORMATION

Part No.

K4S561632D-TC/L60

K4S561632D-TC/L7C

K4S561632D-TC/L75

K4S561632D-TC/L1H

K4S561632D-TC/L1L

Max Freq. Interface Package

166MHz(CL=3)

133MHz(CL=2)

133MHz(CL=3)

100MHz(CL=2)

LVTTL

54pin

TSOP(II)

100MHz(CL=3)

Data Input Register

CLK

ADD

Bank Select

4M x 16

4M x 16

4M x 16

4M x 16

Column Decoder

LCKE

LRAS LCBR

LWE

LCAS

Latency & Burst Length

Programming Register

LWCBR

Timing Register

LWE

LDQM

DQi

LDQM

CLK

CKE

CS

RAS

CAS

WE L(U)DQM

* Samsung Electronics reserves the right to change products or specification without notice.

Rev. 0.1 Aug. 2002

Share Link: