K4S561632J データシートの表示（PDF） - Samsung
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K4S561632J Datasheet PDF : 15 Pages
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K4S560432J
K4S560832J
K4S561632J
13.0 AC Operating Test Conditions
Parameter
AC input levels (VIH/VIL)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
3.3V
Value
2.4/0.4
1.4
tr/tf = 1/1
1.4
See Fig. 2
Output
870Ω
1200Ω
50pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Output
Synchronous DRAM
(VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Unit
V
V
ns
V
Z0 = 50Ω
VTT = 1.4V
50Ω
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
14.0 Operating AC Parameter
(AC operating conditions unless otherwise noted)
Parameter
Version
Symbol
50 (x16 only) 60 (x16 only)
75
Unit Note
Row active to row active delay
RAS to CAS delay
Row precharge time
tRRD(min)
10
12
15
ns
1
tRCD(min)
15
18
20
ns
1
tRP(min)
15
18
20
ns
1
Row active time
Row cycle time
tRAS(min)
37.5
42
tRAS(max)
100
tRC(min)
55
60
45
ns
1
us
65
ns
1
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
tRDL(min)
tDAL(min)
tCDL(min)
2
2 CLK + tRP
1
CLK
2,5
-
5
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
Number of valid output data
CAS latency=3
CAS latency=2
2
ea
4
-
1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
6. tRC =tRFC, tRDL = tWR.
11 of 15
Rev. 1.22 August 2008
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