K9HBG08U1M-P データシートの表示（PDF） - Samsung

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K9HBG08U1M-P

2G x 8 Bit / 4G x 8 Bit NAND Flash Memory

Samsung 

K9HBG08U1M

K9LAG08U0M K9MCG08U5M

Advance

FLASH MEMORY

Product Introduction

The K9LAG08U0M is a 16,384Mbit(17,179,869 bit) memory organized as 1,048,576 rows(pages) by 2,112x8 columns. Spare 64x8

columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays for accom-

modating data transfer between the I/O buffers and memory cells during page read and page program operations. The memory array

is made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block

consists of two NAND structured strings. A NAND structure consists of 32 cells. A cell has 2-bit data. Total 1,081,344 NAND cells

reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block

basis. The memory array consists of 8,192 separately erasable 256K-byte blocks. It indicates that the bit by bit erase operation is pro-

hibited on the K9LAG08U0M.

The K9LAG08U0M has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades

to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by

bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch

Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For

example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block

erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 1G-byte physical space

requires 30 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that

order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase oper-

ation, however, only three row address cycles are used. Device operations are selected by writing specific commands into the com-

mand register. Table 1 defines the specific commands of the K9LAG08U0M.

The K9HBG08U1M is composed of two K9LAG08U0M chips which are selected separately by each CE1 and CE2 and the

K9MCG08U5M is composed of four K9LAG08U0M chips which are selected seperately by each CE1, CE2, CE3 and CE4. Therefore,

in terms of each CE, the basic operations of K9HBG08U0M and K9MBCG08U5M are same with K9LAG08U0M except some AC/DC

charateristics.

Table 1. Command Sets

Function

Read

Read ID

Reset

Page Program

Two-Plane Page Program(2)

Block Erase

Two-Plane Block Erase

Random Data Input(1)

Random Data Output(1)

Read Status

Chip1 Status(3)

Chip2 Status(3)

1st. Cycle

00h

90h

FFh

80h

80h----11h

60h

60h----60h

85h

05h

70h

F1h

F2h

2nd. Cycle

30h

-

-

10h

81h----10h

D0h

D0h

-

E0h

Acceptable Command during Busy

O

O

O

O

NOTE : 1. Random Data Input/Output can be executed in a page.

2. Any command between 11h and 81h is prohibited except 70h and FFh.

3. Interleave-operation between two chips is allowed.

It’s prohibited to use F1h and F2h commands for other operations except interleave-operation.

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

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