K9HBG08U1M データシートの表示（PDF） - Samsung

部品番号

コンポーネント説明

メーカー

K9HBG08U1M

2G x 8 Bit / 4G x 8 Bit NAND Flash Memory

Samsung 

K9HBG08U1M

K9LAG08U0M K9MCG08U5M

Advance

FLASH MEMORY

PIN DESCRIPTION

Pin Name

I/O0 ~ I/O7

Pin Function

DATA INPUTS/OUTPUTS

The I/O pins are used to input command, address and data, and to output data during read operations. The I/

O pins float to high-z when the chip is deselected or when the outputs are disabled.

COMMAND LATCH ENABLE

CLE

The CLE input controls the activating path for commands sent to the command register. When active high,

commands are latched into the command register through the I/O ports on the rising edge of the WE signal.

ADDRESS LATCH ENABLE

ALE

The ALE input controls the activating path for address to the internal address registers. Addresses are

latched on the rising edge of WE with ALE high.

CE / CE1

CHIP ENABLE

The CE / CE 1 input is the device selection control. When the device is in the Busy state, CE / CE1 high is

ignored, and the device does not return to standby mode in program or erase operation.

Regarding CE / CE1 control during read operation , refer to ’Page Read’ section of Device operation

CE2

CHIP ENABLE

The CE2 input enables the second K9LAG08U0M

READ ENABLE

RE

The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid

tREA after the falling edge of RE which also increments the internal column address counter by one.

WRITE ENABLE

WE

The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of

the WE pulse.

WRITE PROTECT

WP

The WP pin provides inadvertent program/erase protection during power transitions. The internal high volt-

age generator is reset when the WP pin is active low.

R/B / R/B1

READY/BUSY OUTPUT

The R/B / R/B1 output indicates the status of the device operation. When low, it indicates that a program,

erase or random read operation is in process and returns to high state upon completion. It is an open drain

output and does not float to high-z condition when the chip is deselected or when outputs are disabled.

Vcc

POWER

VCC is the power supply for device.

Vss

GROUND

N.C

NO CONNECTION

Lead is not internally connected.

NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.

Do not leave VCC or VSS disconnected.

There are two CE pins (CE1 & CE2) in the K9HBG08U1M and four CE pins (CE1 & CE2 & CE3 & CE4) in the K9MCG08U5M.

There are two R/B pins (R/B1 & R/B2) in the K9HBG08U1M and four R/B pins (R/B1 & R/B2 & R/B3 & R/B4) in the

K9MCG08U5M.

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