SST39SF512_03 データシートの表示（PDF） - Silicon Storage Technology
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SST39SF512_03 Datasheet PDF : 22 Pages
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Data Sheet
Device Operation
Commands are used to initiate the memory operation func-
tions of the device. Commands are written to the device
using standard microprocessor write sequences. A com-
mand is written by asserting WE# low while keeping CE#
low. The address bus is latched on the falling edge of WE#
or CE#, whichever occurs last. The data bus is latched on
the rising edge of WE# or CE#, whichever occurs first.
Read
The Read operation of the SST39SF512 is controlled by
CE# and OE#, both have to be low for the system to obtain
data from the outputs. CE# is used for device selection.
When CE# is high, the chip is deselected and only standby
power is consumed. OE# is the output control and is used
to gate data from the output pins. The data bus is in high
impedance state when either CE# or OE# is high. Refer to
the Read cycle timing diagram for further details (Figure 4).
Byte-Program Operation
The SST39SF512 are programmed on a byte-by-byte
basis. Before programming, the sector where the byte
exists must be fully erased. The Program operation is
accomplished in three steps. The first step is the three-byte
load sequence for Software Data Protection. The second
step is to load byte address and byte data. During the Byte-
Program operation, the addresses are latched on the falling
edge of either CE# or WE#, whichever occurs last. The
data is latched on the rising edge of either CE# or WE#,
whichever occurs first. The third step is the internal Pro-
gram operation which is initiated after the rising edge of the
fourth WE# or CE#, whichever occurs first. The Program
operation, once initiated, will be completed, within 30 µs.
See Figures 5 and 6 for WE# and CE# controlled Program
operation timing diagrams and Figure 15 for flowcharts.
During the Program operation, the only valid reads are
Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any
commands written during the internal Program operation
will be ignored.
Sector-Erase Operation
The Sector-Erase operation allows the system to erase the
device on a sector-by-sector basis. The sector architecture
is based on uniform sector size of 4 KByte. The Sector-
Erase operation is initiated by executing a six-byte com-
mand load sequence for Software Data Protection with
Sector-Erase command (30H) and sector address (SA) in
the last bus cycle. The sector address is latched on the fall-
ing edge of the sixth WE# pulse, while the command (30H)
is latched on the rising edge of the sixth WE# pulse. The
512 Kbit Multi-Purpose Flash
SST39SF512
internal Erase operation begins after the sixth WE# pulse.
The end of Erase can be determined using either Data#
Polling or Toggle Bit methods. See Figure 9 for timing
waveforms. Any commands written during the Sector-
Erase operation will be ignored.
Chip-Erase Operation
The SST39SF512 provide Chip-Erase operation, which
allows the user to erase the entire memory array to the “1s”
state. This is useful when the entire device must be quickly
erased.
The Chip-Erase operation is initiated by executing a six-
byte Software Data Protection command sequence with
Chip-Erase command (10H) with address 5555H in the last
byte sequence. The Erase operation begins with the rising
edge of the sixth WE# or CE#, whichever occurs first. Dur-
ing the Erase operation, the only valid read is Toggle Bit or
Data# Polling. See Table 4 for the command sequence,
Figure 10 for timing diagram, and Figure 18 for the flow-
chart. Any commands written during the Chip-Erase opera-
tion will be ignored.
Write Operation Status Detection
The SST39SF512 provide two software means to detect
the completion of a Write (Program or Erase) cycle, in
order to optimize the system Write cycle time. The software
detection includes two status bits: Data# Polling (DQ7) and
Toggle Bit (DQ6). The End-of-Write detection mode is
enabled after the rising edge of WE#, which initiates the
Program or Erase cycle.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to
conflict with either DQ7 or DQ6. In order to prevent spuri-
ous rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed loca-
tion an additional two (2) times. If both reads are valid,
then the device has completed the Write cycle, otherwise
the rejection is valid.
©2003 Silicon Storage Technology, Inc.
2
S71149-05-000
11/03
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