NHI-15191RT データシートの表示（PDF） - Unspecified

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NHI-15191RT

Multi-Protocol Data Bus Interface NHi-RT Expanded Memory Remote Terminals

Unspecified 

3.2.0

BLOCK DIAGRAM

The NHi- RTs contains two +5 volt transceivers, an ASIC, and an SRAM. The ASIC performs all

multi protocol functions of a REMOTE TERMINAL. It controls accesses to the RAM such that it

appears to the host CPU 16bit wide dual port memory.

Since the NHi- RT appears to its host as RAM, no external logic is required when interfacing to

the device. It is simply connected to the CPU's address bus, Mil Bus, and control lines. There are

NO EPROMS required to illegalize commands. Illegalization is performed internal to the protocol

chip in the NHi- RT.The user sets up command illegalization when the NHi- RT is initialized. See

sections on Message Illegalization and Host Initialization.

BUS_A

BUS_A_L

TXINH_A

BUS_B

BUS_B_L

TXINH_B

TRANSCEIVER

CHANNEL A

TRANSCEIVER

CHANNEL B

PROTOCOL

REMOTE TERMINAL

CMDS

MDCDRST

PLSCMD

SSF_TF

H_DAT(15:0)

H_ADR(14:1)

HCS_L

HRD_L

HWRH_L

HWRL_L

DTACK_L

IRQ_L

INTACK_L

DSC_INTPO_L

INTPI_L

MRST_L

CLK

I/O_WR_L

I/O_RD_L

SRAM

I/O_ADR(2:1)

I/O_DAT(7:0)

NHi-RT EXPANDED MEMORY FUNCTIONAL BLOCK DIAGRAM

The NHi- RT can be interfaced to an 8 bit data bus by folding the upper and lower bytes on top of

each other and performing byte wide data transfers.

By default, the host has priority in accessing the I/ O bus. When the host requests access to a

device already in use by the protocol chip, the host *DTACK signal is delayed by the NHi- RT. If

either side (protocol chip or host) waits for access during the current cycle, it is automatically

granted priority for the next cycle. The host can retain priority for successive cycles accessing the

same address (this is required to guarantee the proper operation of host read- modify- write

instructions - see pin *HCS for details) by keeping *HCS low.

3.3.0

PROTOCOL CHIP DESCRIPTION

The protocol chip contains the following modules:

Host Bus Interface Unit

I/ O Bus Interface Unit

Interrupt Controller Unit

Dual Redundant Multi Protocol Front End

Message Processor Unit

(HBIU)

(IBIU)

(ICU)

(DRFE)

(MPU)

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