NHI-15191RT データシートの表示（PDF） - Unspecified

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NHI-15191RT

Multi-Protocol Data Bus Interface NHi-RT Expanded Memory Remote Terminals

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3.3.1

HOST BUS INTERFACE UNIT

The HBIU provides a standard RAM interface to the host bus. The module performs the following

functions:

Provides NHi- RT device select and decodes host address to select registers.

Transfers data between the NHi-RT and the host (word and byte mode as well as read-

modify- write are supported).

Provides priority input and output for daisy chaining host interrupts.

Outputs *DTACK signal indicating end of bus cycle.

3.3.2

I/O BUS INTERFACE UNIT

The IBIU controls the RAM and I/ O residing on the I/ O bus so that it appears to the host as a

pseudo dual port RAM (i. e., shared memory). The unit implements the following functions:

Arbitrates between host and protocol chip initiated accesses to the RAM and host data

bus.

Decodes address lines to select device (e. g. RAM, external byte- wide I/ O, external

terminal address buffer, command output register).

Generates control signals to access the selected device.

3.3.3

INTERRUPT CONTROL UNIT

The ICU is an 8 input vectored interrupt controller. It contains eight registers as well as a FIFO for

storing pending interrupt vectors.

3.3.3.1 ICU REGISTERS

The ICU contains the following registers

INTERRUPT REQUEST register

INTERRUPT MASK register

INTERRUPT VECTOR register

AUXILIARY VECTOR register

(IRR)

(IMR)

(IVR)

(AVR)

The INTERRUPT REQUEST register samples 8 inputs originating from internal modules. Since

the host can write to this register, all interrupt sequences can be software driven for program

debugging. The inputs and their priorities (level 7 has highest priority) are described in the

following table.

3.3.3.1.1 INTERRUPT DEFINITION TABLE

PRIORITY

0

1

2

3

4

5

6

7

RTU INTERRUPT

VALID TX/RX EOM

INVALID TX/RX EOM

VALID MODE CODE

INVALID MODE CODE

FIFO OVERFLOW

VALID BROADCAST

INVALID BROADCAST

FAILSAFE TIMEOUT

Note: RT Interrupts 5 & 6 are enabled only when separate Broadcast Tables are used.

Masking interrupt 4 creates a revolving Fifo.

As soon as an interrupt is requested, its vector is pushed onto the FIFO - so the chronological

-7-

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