NHI-15191RT データシートの表示（PDF） - Unspecified
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NHI-15191RT Datasheet PDF : 54 Pages
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order of the requests normally determines the order in which they will be serviced. Simultaneous
requests, however, are pushed onto the FIFO according to the priority of the pending interrupts.
The INTERRUPT MASK register masks the corresponding inputs to the INTERRUPT REQUEST
register. The INTERRUPT VECTOR register holds the 3 bit interrupt priority level and an
additional 5 bit field (see paragraph on INTERRUPT VECTOR register for details).
The AUXILIARY VECTOR register contains an additional byte of information related to the
interrupt request (see paragraph on AUXILIARY VECTOR register for details).
3.3.3.2 ICU FIFO
The ICU FIFO is 16 bits wide and 7 words deep. Whenever an unmasked interrupt request is
issued by the message processor, a word is pushed onto the FIFO. When an interrupt is
acknowledged by the host, a word is popped from the FIFO and used to update the IVR and the
AVR.
The host can read the FIFO by simply popping its contents. This is done by reading the FIFO
located at address 8 (refer to address map). The interrupt request output, *IRQ, will go inactive
after the FIFO is emptied in this way.
The host can mask the *IRQ output by resetting the INTERRUPT REQUEST ENABLE bit in the
CONTROL register; however this does not prevent the device from pushing interrupt requests
onto the FIFO.
If an interrupt request occurs when the FIFO is full, a vector indicating FIFO overflow is first
pushed onto the FIFO and then the vector which caused the overflow is pushed onto the FIFO.
As a result, the 2 oldest vectors are lost. All further pushes are then inhibited until the host pops
the vector indicating the overflow.
The above mechanism ensures that the host will always be notified of FIFO overflows and will
always obtain the 2 interrupt vectors immediately preceding the overflow condition.
If interrupt 4 is masked, the FIFO operates in the revolving mode; vectors are continuously
pushed onto the FIFO. After the 7th vector is pushed without any pops, each additional vector
pushed causes the oldest vector to be lost.
The FIFO can be emptied by writing (any value) to address 8 (in words).
3.3.4
DUAL REDUNDANT FRONT END
The DRFE performs serial to parallel and parallel to serial conversion as well as basic format and
timing validation. The unit contains the following:
Manchester encoders/ decoders
Gap counter
No response counter
Minimum response time counter
Timeout counter
3.3.4.1 MANCHESTER DECODER
The decoder translates serial Manchester bi- phase signals to 16- bit words and outputs the
following signals:
Valid command word received
Valid data word received
Invalid word received (parity, incorrect bit count, invalid Manchester encoding, gap)
Broadcast command received
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