7. BLOCK DIAGRAM
CN1
Buf f er
FLM
CL1
CL2
DISP•OFF
UD7~
UD0
Buf f er
LD7~
LD0
Buf f er
Timing M
Circuit
Timing
Circuit
DISP•OFF
Column driv ing circuit (Upper)
X1
LCD PANEL
X480
Column driv ing circuit (Lower)
VDD
VSS
VCON
Pow er
Supply
Circuit
CN2
CFL
VCFL
VSS
CN3
4 X1
3 Y1
2 X2
1 Y2
Y1
X2 Touch Screen X1
Y2
* Reference of touch panel pin connection.
Dis p l a ys ,
Hitachi, Ltd. Date Nov. 4, '99
Sh.
No.
3284PS 2707 - SX21V001-Z4 - 4
Page 7-1/1