74F175 データシートの表示（PDF） - Fairchild Semiconductor
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74F175 Datasheet PDF : 7 Pages
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Unit Loading/Fan Out
Pin Names
Description
D0–D3
CP
MR
Q0–Q3
Q0–Q3
Data Inputs
Clock Pulse Input (Active Rising Edge)
Master Reset Input (Active LOW)
True Outputs
Complement Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−1 mA/20 mA
−1 mA/20 mA
Functional Description
The 74F175 consists of four edge-triggered D-type flip-
flops with individual D inputs and Q and Q outputs. The
Clock and Master Reset are common. The four flip-flops
will store the state of their individual D inputs on the
LOW-to-HIGH clock (CP) transition, causing individual Q
and Q outputs to follow. A LOW input on the Master Reset
(MR) will force all Q outputs LOW and Q outputs HIGH
independent of Clock or Data inputs. The 74F175 is useful
for general logic applications where a common Master
Reset and Clock are acceptable.
Truth Table
Inputs
MR
CP
Dn
L
X
X
H
H
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Outputs
Qn
Qn
L
H
H
L
L
H
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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