FS61857-01 データシートの表示（PDF） - AMI Semiconductor

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FS61857-01

1:10 HSTL Zero-Delay Clock Buffer IC

AMI Semiconductor 

FS61857-01

1:10 HSTL Zero-Delay Clock Buffer IC

Advance Information

AMERICAN MICROSYSTEMS, INC.

November 2000

Table 2: Pin Descriptions

Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,

DO = Digital Output; P = Power/Ground; # = Active Low pin

PIN

TYPE

16

P

17

P

13 / 14

DI

36 / 35

DI

32 / 33

DO

37

DI

3/2

5/6

10 / 9

20 / 19

22 / 23

DO

46 / 47

44 / 43

39 / 40

29 / 30

27 / 26

1, 7, 8, 18, 24, 25,

31, 41, 42, 48

P

4, 11, 12, 15, 21,

28, 34, 38, 45

P

NAME

AVDD

AGND

CKP / CKN

FBINP / FBINN

FBOUTP / FBOUTN

PWRDWN#

YP0 / YN0

YP1 / YN1

YP2 / YN2

YP3 / YN3

YP4 / YN4

YP5 / YN5

YP6 / YN6

YP7 / YN7

YP8 / YN8

YP9 / YN9

GND

DESCRIPTION

2.5V PLL power supply / Test mode enable.

This pin provides the power supply to the internal PLL. When pulled low, the PLL is by-

passed and the output clocks directly follow the input clock

PLL ground

Reference clock input (true / complementary)

Feedback input (true / complementary)

Feedback output (true / complementary)

Asynchronous power-down input shuts down PLL and tristates all outputs

Clock outputs (true / complementary)

Ground for all clock outputs

VDD

2.5V power supply for all clock outputs

3.0 Device Operation

3.1 PLL Bypass

The FS61857 precisely aligns the frequency and phase

of the differential HSTL output clocks to the differential

reference input CKP/CKN by use of an on-chip phase-

lock loop (PLL). The PLL generates 10 low-skew, low-

jitter copies of the reference, with the outputs adjusted for

50% duty cycle.

When the AVDD pin is pulled low, the reference clock

signal bypasses the PLL and is muxed directly through to

the outputs. The PLL is powered down, and device acts a

fanout buffer. Note that if AVDD is re-established, the

PLL requires a power-up and stabilization time to lock to

the input clock.

The differential FBOUT clock must be hardwired to the

FBINP/FBINN pins to complete the loop. The PLL ac-

tively adjusts the output clocks so that there is no phase

error between the reference clock and the feedback in-

put.

Since the device uses a PLL to lock the output clocks to

the input clock, there is a power-up stabilization time that

is required for the PLL to achieve phase lock.

3.2 Power-Down

The FS61857 provides an auto power-down feature that

shuts off the PLL and tristates all outputs low if the refer-

ence clock drops below 20MHz. The power-down circuit

is level sensitive, and detects either a DC high or low on

the CKP/CKN input pair. If the input clock rises above

20MHz, the PLL powers back up to re-establish lock.

Note that all inputs and outputs use 2.5V HSTL signal An asynchronous active-low PWRDWN# signal also

levels.

places the part in the power off state.

ISO9001

QS9000

2

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