FS61857-01 データシートの表示（PDF） - AMI Semiconductor

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FS61857-01

1:10 HSTL Zero-Delay Clock Buffer IC

AMI Semiconductor 

AMERICAN MICROSYSTEMS, INC.

November 2000

FS61857-01

1:10 HSTL Zero-Delay Clock Buffer IC

Advance Information

Table 6: AC Timing Specifications

Unless otherwise stated, all power supplies = 2.5V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and

are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σ f rom typical.

PARAMETER

SYMBOL

CONDITIONS/DESCRIPTION

MIN.

TYP. MAX. UNITS

Overall

Clock Skew, Output to Output *

Dynamic Phase Offset

Static Phase Offset

Clock Stabilization Time *

Phase-Lock Loop

Loop Bandwidth *

Phase Angle *

Phase Error *

Clock Outputs (1Y0:9, FBOUT)

Duty Cycle *

Jitter, Cycle-cycle *

(peak-peak)

Jitter, Period *

(peak-peak)

Jitter, Half-Period *

(peak-peak)

Rise Time *

Fall Time *

Enable Delay *

Disable Delay *

tsk(o)

Measured VX between two output pairs CL = 15pF

Spread modulation ON

tdΦ

Spread modulation ON

tΦ

Does not include jitter

Time required for the PLL to achieve phase lock

For calculation of Tracking Skew

For calculation of Tracking Skew

From rising edge on CLK to rising edge on FBIN

dt

tj(CC)

tj(∆P)

tj(∆½P)

tr

tf

tDLH

tDHL

VO = 0.5V to 2.0V; CL = 15pF

VO = 2.0V to 0.5V; CL = 15pF

via PWRDWN#

via PWRDWN#

-120

2.0

45

-75

-75

-100

0.75

0.75

ps

ps

120

ps

ms

-0.031

MHz

°

ps

55

%

75

ps

75

ps

100

ps

1.5

ns

1.5

ns

ns

ns

ISO9001

QS9000

5

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