DM9102A データシートの表示（PDF） - Davicom Semiconductor, Inc.

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DM9102A

Single Chip Fast Ethernet NIC Controller

Davicom Semiconductor, Inc. 

DM9102A

Single Chip Fast Ethernet NIC Controller

5.3 LED Pins (Please refer to “Note: LED Mode” for details)

Pin No.

Pin Name

I/O

Description

128QFP/128LQFP

87

LINK&ACT#

O LED Output Pin, Active Low

/ ACT#

mode 0 = Link and traffic LED. Active low to indicate normal

link, and it will flash as a traffic LED when transmitting or

receiving

mode 1 = traffic LED only

88

FDX#

O LED Output Pin, Active Low

/ FDX#

mode 0 = Full duplex LED

mode 1 = Full duplex LED

89

SPEED100#

O LED Output Pin, Active Low

/ SPEED100#

mode 0 = 100Mbps LED

mode 1 = 100Mbps LED

90

SPEED10#

O LED Output Pin, Active Low

/ LINK#

mode 0 = 10Mbps LED

mode 1 = Link LED

5.4 Network Interface

Pin No.

128QFP/128LQFP

105,106

109,110

Pin Name

RXI+

RX-

TXO+

TXO-

I/O

Description

I 100M/10Mbps Differential Input Pair

These two pins are differential receive input pair for 100BASE-

TX and 10BASE-T. They are capable of receiving 100BASE-

TX MLT-3 or 10BASE-T Manchester encoded data

O 100M/10Mbps Differential Output Pair

These two pins are differential output pair for 100BASE-TX

and 10BASE-T. This output pair provides controlled rise and

fall times designed to filter the transmitter output

5.5 Miscellaneous Pins

Pin No.

128QFP/128LQFP

36

71

75

95

10

Pin Name

CLOCKRUN#

TEST2

TEST1

WOL

I/O

Description

I/O, Clockrun#

O/D The clockrun# signal is used by the system to pause or slow

down the PCI clock signal. It is used by the DM9102A to

enable or disable suspension of the PCI clock signal or restart

of the PCI clock. When the clockrun# signal is not used, this pin

should be connected to an external pull-down resistor

I TEST Mode Control 2

In normal operation, this pin is pulled-high

I TEST Mode Control 1

In normal operation, this pin is pulled low

O Wake Up Signal

Final

Version: DM9102A-DS-F07

April 12, 2002

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