IMP1232LP データシートの表示（PDF） - IMP, Inc

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IMP1232LP

5V µP Power Supply Monitor and Reset Circuit

IMP, Inc 

IMP1232LP/LPS

Absolute Maximum Ratings

Voltage on VCC . . . . . . . . . . . . . . . . . . . . . . . . –0.5V to 7V

Voltage on ST, TD . . . . . . . . . . . . . . . . . . . . . –0.5V to VCC + 0.5V

Voltage on PBRST, RESET, RESET . . . . . . . . –0.5V to VCC + 0.5V

Operating Temperature Range . . . . . . . . . . . –40°C to 85°C

(N/EMA version)

0°C to 70°C

Soldering Temperature . . . . . . . . . . . . . . . . . . 260°C for 10 seconds

Storage Temperature . . . . . . . . . . . . . . . . . . . –55°C to 125°C

Voltages measured with respect to ground.

These are stress ratings only and functional operation is not implied.

Electrical Characteristics

Unless otherwise stated, 4.5V ≤ VCC ≤ 5.5V and over the operating temperature range of 0°C to +70°C (–40°C to +85°C for N/EMA

devices). All voltages are referenced to ground.

Parameter

Symbol Conditions

Min

Typ

Max

Units

Supply Voltage (VCC)

ST and PBRST Input High Level

ST and PBRST Input Low Level

VCC Trip Point (TOL = GND)

VCC Trip Point (TOL = VCC)

Watchdog Time-Out Period

Watchdog Time-Out Period

Watchdog Time-Out Period

Output Voltage

Output Current

Output Current

Input Leakage

RESET Low Level

Internal Pull-Up Resistor

VCC

VIH

VIL

VCCTP

VCCTP

tTD

tTD

tTD

VOH

IOH

IOL

IIL

VOL

TD = GND

TD = VCC

TD floating

I = –500µA, Note 3

Output = 2.4V , Note 2

Output = 0.4V,

Note 1

Note 1

4.5

5.5

V

2

– 0.3

VCC + 0.3V

V

0.8

V

4.50

4.62

4.74

V

4.25

4.37

4.49

V

62.5

150

250

ms

500

1200

2000

ms

250

610

1000

ms

VCC - 0.5V VCC - 0.1V

V

–8

–10

mA

10

mA

–1.0

1.0

µA

0.4

V

40

kΩ

Operating Current (CMOS)

ICC1

Input Capacitance

CIN

Output Capacitance

COUT

PBRST Manual Reset

tPB

PBRST = VIL

20

Minimum Low Time

30

µA

5

pF

10

pF

ms

Reset Active Time

ST Pulse Width

VCC Fail Detect to

RESET or RESET

tRST

tST

tRPD

Note 4

250

610

1000

ms

20

ns

5

8

µs

VCC Slew Rate

tF

4.75V to 4.25V

300

PBRST Stable LOW to

tPDLY

RESET and RESET Active

µs

20

ms

VCC Detect to RESET or

RESET Inactive

tRPU

tRISE = 5µs

250

610

1000

ms

VCC Slew Rate

tR

4.25V to 4.75V

0

ns

Notes: 1. PBRST is internally pulled HIGH to VCC through a nominal 40kΩ resistor.

2. RESET is an open drain output.

3. RESET remains within 0.5V of VCC on power-down until VCC falls below 2V. RESET remains within 0.5V of ground on power-down

until VCC falls below 2.0V.

4. Must not exceed the minimum watchdog time-out period (tTD). The watchdog circuit cannot be disabled. To avoid a reset, ST must be

strobed.

© 1999 IMP, Inc.

408-432-9100/www.impweb.com

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