5962F9563501QXC データシートの表示（PDF） - Intersil
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5962F9563501QXC Datasheet PDF : 36 Pages
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Block Diagram
CONTROL
INPUTS
INTERRUPT
INPUTS
TIMER
INPUTS
HS-RTX2010RH
OFF CHIP
PERIPHERALS
MAIN
MEMORY
CLOCK AND
CONFIGURATION
CONTROL
INTERRUPT
CONTROL
TIMER/
COUNTERS
BARREL
SHIFTER
ASIC BUS
INTERFACE
MEMORY BUS
INTERFACE
HS-RTX2010RH
MEMORY
PAGE
CONTROL
RTX CORE
PROCESSOR
MAC
256-WORD
RETURN
STACK
256-WORD
PARAMETER
STACK
STACK
CONTROLLERS
Pinouts
HS8-RTX2010RH
MIL-STD-1835 CMGA3-P85C
A B CDE F GH J K L
11 MD08 MD07 MD06 GND MD02 MD01 PCLK UDS GND MA19 MA16
10 MD11 MD09 VDD MD05 MD03 NEW BOOT LDS MA18 MA17 MA14
9 MD12 MD10
MD04 MD00 MR/W
MA15 VDD
8 MD14 MD13
7 GA00 MD15 GA01
6 TCLK GND GA02
5 INTA
NMI
INT-
SUP
4 VDD E I1
HS-RTX2010RH
TOP VIEW
PINS DOWN
MA13 MA12
GND MA10 MA09
MA08 MA07 MA11
MA04 MA05 MA06
MA02 MA03
3 E I2 E I4
GD14 GD11 GD10
GD01 MA01
2 E I3 RESET WAIT GIO GD13 GD12 GD08 GD06 GD03 GD02 GD00
1 E I5 ICLK GR/W GD15 GND GD07 GD09 VDD GD05 GD04 GND
L K J H G F E D C BA
11
MA16 MA19 GND UDS PCLK MD01 MD02 GND MD06 MD07 MD08
10
MA14 MA17 MA18 LDS BOOT NEW MD03 MD05 VDD MD09 MD11
9
VDD MA15
MR/W MD00 MD04
MD10 MD12
8
MA12 MA13
MD13 MD14
7
MA09 MA10 GND
BOTTOM VIEW
GA01 MD15 GA00
6
MA11 MA07 MA08
PINS UP
GA02 GND TCLK
5
MA06 MA05 MA04
MA03 MA02
MA01 GD01
GD10 GD11 GD14
INTSUP NMI INTA
4
ALIGN.
PIN
E I1
VDD
3
E I4 E I2
2
GD00 GD02 GD03 GD06 GD08 GD12 GD13 GIO WAIT RESET E I3
1
GND GD04 GD05 VDD GD09 GD07 GND GD15 GR/W ICLK E I5
A B CDE F GH J K L
L K J H G F E D C BA
PIN
PIN
A1
A1
NOTE: An overbar on a signal name represents an active LOW signal.
2
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