74LVC821A データシートの表示（PDF） - Philips Electronics
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74LVC821A
Philips Electronics
74LVC821A Datasheet PDF : 12 Pages
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Philips Semiconductors
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
Product specification
74LVC821A
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V.
VOL and VOH are the typical output voltage drop that occur with the
output load.
VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V
VY = VOH –0.3V at VCC w 2.7V; VY = VOH – 0.1 VCC at VCC t 2.7V
VI
CP INPUT
GND
VOH
Qn OUTPUT
VOL
1/fmax
VM
VM
tw
tPHL
VM
VM
tPLH
VM
SA00394
Figure 1. Clock (CP) to output (Qn) propagation delays, the
clock pulse width and the maximum clock pulse frequency.
VI
OE INPUT
VM
GND
VCC
OUTPUT
LOW-to-OFF
OFF-to-LOW
VOL
tPLZ
VX
tPZL
VM
VOH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
tPHZ
outputs
enabled
tPZH
VY
outputs
disabled
VM
outputs
enabled
SA00412
Figure 2. 3-State enable and disable times.
VI
CP
INPUT
VM
GND
tsu
tsu
VI
ÉÉÉÉ Dn
ÉÉÉÉ INPUT
VM
ÉÉÉÉ GND
ÉÉÉth ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉth ÉÉÉ
VOH
Qn
OUTPUT
VM
VOL
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
SW00229
Figure 3. Data setup and hold times for the Dn input to the CP
input.
TEST CIRCUIT
VI
PULSE
GENERATOR
VCC
D.U.T.
RT
VO
CL 50pF
S1
500Ω
2 x VCC
Open
GND
500Ω
VCC
t 2.7V
2.7V – 3.6V
VI
VCC
2.7V
Test
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2 x VCC
GND
SY00003
Figure 4. Load circuitry for switching times.
1998 Sep 25
7
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