ACS760ELF-20B(2013) データシートの表示（PDF） - Allegro MicroSystems
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ACS760ELF-20B
(Rev.:2013)
(Rev.:2013)
Allegro MicroSystems
ACS760ELF-20B Datasheet PDF : 15 Pages
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ACS760ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC
Hard Short Circuit (50 mΩ from VLOAD to GND)
Fault Operation
The timing diagram below specifically shows characteristic
operation of the ACS760 when the device is powered on (via the
EN pin) and a 50 m short circuit is present from load side of the
external MOSFET, S1, to ground.
ISC , is greater than 100 A, then the OCDLY pin will reach the
3.85 V threshold before the current through the external MOS-
FET exceeds ISC. This is the case depicted in the panel A. The
fault event is detected at tGATE_LOW. At this time. the FAULT
signal transitions to the low state and the GATE pin is pulled to
ground.
In figure 3 the system power supply bus reaches the nominal
steady state level of 12 V before the EN pin of the ACS760 tran-
sitions to the high state at time tEN1. The voltage on the GATE
pin increases with a positive slope after the EN pin transitions to
the high state. The ramp rate of the GATE pin is controlled by the
value of the capacitor connected to the CG pin. In the example
shown below a small capacitor is connected to the CG pin and the
pin ramps to 5.5 V in < 10 s.
In panel A of figure 3, the device is enabled into a 50 m short
circuit. Therefore, as the GATE voltage increases the current
through the external MOSFET increases at a rapid rate. In this
example case it is assumed that there is no capacitor on the
OCDLY pin. When the current through the MOSFET exceeds the
threshold set by the RSET resistor, the voltage on the OCDLY pin
rises quickly beginning at t40A_F. As the voltage on the OCDLY
pin rises, so does the voltage on the CG pin and the current
through the external MOSFET. If there is no capacitor on the
OCDLY pin, and if the ACS760 Short Circuit Fault Threshold,
In the event that a large capacitor is connected to the OCDLY pin,
the ACS760 will not pull down the gate of the external MOS-
FET until the current flowing through the MOSFET exceeds ISC
(shown in panel B, under the assumption that ISC equals 130 A).
The device pulls down the MOSFET GATE approximately 2 s
after the load current exceeds this threshold. If a large capacitor
is connected to the OCDLY pin a significant current (> 40 A but
< 160 A) may flow through the MOSFET for tens of microsec-
onds before the Short Circuit Fault Threshold trips. These tens
of microseconds elapse as the GATE charges and the load current
increases, finally exceeding the short circuit threshold.
The FAULT signal is latched and the chip will pull down the
GATE voltage until the EN pin of the ACS760 transitions to the
low state and then back to the high state. Certain ACS760 signals
(soft start and fault monitoring) are reset when the EN pin transi-
tions to the low state. These signals are reset in order to guarantee
normal device operation when the EN signal transitions to the
high state.
5.25 V
0.4 V
0A
100 A
40 A
0V
3.3 V
VIOUT Voltage
Load Current / IP
GATE Voltage
FAULT
≈0 V
0V
0V
3.85 V threshold
0V
3.85 V threshold
0V
12 V
tEN1 t40A_F
EN
CG Pin Voltage
VLOAD to Load
OPDLY Pin Voltage
OCDLY Pin Voltage
12 V on IP+ Pins
tGATE_LOW
(A)
1.648 V
0.4 V
5.5 V
5.5 V
19.2 A
22 V
3.3 V
5.5 V
12 V
tRESET
Time
0.4 V
0A
130 A
40 A
0V
3.3 V
VIOUT Voltage
Load Current / IP
GATE Voltage
FAULT
≈0 V
0V
0V
3.85 V threshold
0V
3.85 V threshold
0V
12 V
tEN1 t40A_F
EN
CG Pin Voltage
VLOAD to Load
OPDLY Pin Voltage
OCDLY Pin Voltage
12 V on IP+ Pins
tGATE_LOW_IN < 2μs
t130A_F
(B)
tRESET
Time
Figure 3. (A) Timing Diagram for a 50 mΩ Short Circuit from VLOAD to GND; (B) Timing Diagram for a 50 mΩ Short Circuit from VLOAD to GND, capacitor
COCD with high rating connected.
Allegro MicroSystems, LLC
10
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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