ACS760ELF-20B(2013) データシートの表示（PDF） - Allegro MicroSystems

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ACS760ELF-20B
(Rev.:2013)

12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC

Allegro MicroSystems 

ACS760ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC

S1 Short Fault Operation

The timing diagram in figure 4 shows the characteristic operation

of the ACS760 when the power consumed from the 12 V system

bus exceeds a 240 V*A or 240 W level. For the operation during a

240 V*A fault condition, refer to figure 1. That section describes

the operation of the ACS760 until the time t240VA_F. Figure 4

depicts a 240 V*A fault, but continues on to demonstrate the abil-

ity of the ACS760 to detect damage and improper operation of

the external MOSFET in an S1 short circuit event.

At t240VA_F , the FAULT signal transitions to the low state and the

ACS760 pulls down the voltage on the GATE pin. During normal

0.4 V

0A

1.83 V

22 A

3A

VIOUT Voltage 0.4 V

Load Current / IP 0 A

0V

3.3 V

≈0 V

0V

0V

12 V

3.85 V threshold

0V

0V

12 V

3.3 V

tEN1

tINIT_F

GATE Voltage 0 V

FAULT

EN

CG Pin Voltage

0.4 V

3.3 V

5.5 V

VLOAD to Load 0 V

OPDLY Pin Voltage 5.5 V

OCDLY Pin Voltage 0 V

12 V on IP+ Pins 0 V

S1SHORT Pin

tS1SHORT

t240A_F

0.4 V

tRESET

Time

Figure 4. Timing Diagram for S1 Short

operation, when the GATE pin is at 0 V, the current through the

S1 MOSFET (and therefore through the ACS760) equals approxi-

mately 0 A. However, in the case depicted in figure 4, current

through the S1 MOSFET flows even though the GATE pin is

pulled low. If a FAULT has occurred and more than 2.1 A flow

through the ACS760, then the S1SHORT signal transitions to the

low state. When the S1SHORT signal is low, that indicates to the

system that the ACS760 cannot turn off the external MOSFET

(for example, when a short circuit exists between the source and

the drain of the MOSFET). In the case depicted, the system shuts

down the 12 V power supply after the S1SHORT signal transi-

tions to the low state.

Note that, in some cases, the GATE of the S1 MOSFET may be

shorted to the source or drain of the MOSFET. In this case the

ACS760 may not be able to pull down the gate of the S1 MOS-

FET. However, in this case the ACS760 will still register an S1

Short even if the gate potential is equal to or greater than 12 V.

If the ACS760 is disabled (EN pin in the low state) and greater

than 2.1 A flows through the ACS760, then the device will reg-

ister an S1 Short condition and the S1SHORT pin will transition

to the low state. The voltage on the GATE pin is not used as a

determining factor when sensing an S1 Short condition.

The S1SHORT signal will not reset to a high state until power

to the device is cycled. Toggling the EN pin does not reset the

latched S1 Short state.

Determining the Root Cause of an ACS760 Fault Event

The following truth table provides system debugging information

in the event of a fault event during use of the ACS760. Note that

for all of the fault conditions listed, it is possible to monitor the

voltages of various ACS760 output pins and determine the cause

of the ACS760 FAULT event.

Fault Condition Truth Table

Pin Logic State

FAULT Pin

OPDLY Pin

Low

High

Low

Don’t Care

Low

Low

OCDLY Pin

Low

High

Low

Probable Root Cause

240 V*A system power level, PF(th), exceeded

IP Fault Current Threshold, IPF, exceeded

Short Circuit Fault Threshold, ISC, exceeded

Allegro MicroSystems, LLC

11

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

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