ACS760ELF-20B(2013) データシートの表示（PDF） - Allegro MicroSystems

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ACS760ELF-20B
(Rev.:2013)

12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC

Allegro MicroSystems 

ACS760ELF-20B 12 V High-Side Hot-Swap Hall Effect Based Current Monitor IC

240 V*A Fault Operation

The timing diagram in figure 1 shows characteristic operation

of the ACS760 when the power consumed from the 12 V system

bus exceeds a 240 V*A or 240 W level. The system power supply

bus reaches the nominal steady state level of 12 V before the EN

pin (Enable pin, active high) of the ACS760 transitions to the

high state at time tEN1. Note that, when the EN pin is in the low

state, the GATE pin is actively pulled low. However, as shown

in the timing diagram, the voltage on the GATE pin increases

with a positive slope after the EN pin transitions to the high state.

The ramp rate of the GATE pin is controlled by the value of the

capacitor connected to the CG pin.

At a certain GATE voltage, current begins to flow through the

external protection MOSFET, S1, and this current increases as the

GATE voltage increases. The voltage at the VIOUT pin, which is

the current device output voltage of the ACS760, proportionally

tracks the current that flows through the MOSFET.

In the timing diagram, the system is in normal, steady state opera-

tion up until the time tINIT_F. At tINIT_F , the current load on the

12 V power supply increases from 19.2 to 22 A and the ACS760

internally registers a 240 V*A fault condition. At this time, the

voltage on the OPDLY pin increases with a constant slope. (This

slope is controlled by the value of the capacitor connected to the

OPDLY pin). This voltage continues to increase with a constant

slope until either:

• The OPDLY pin voltage reaches a threshold of 3.85 V (if this

occurs, the FAULT signal is latched in the low state), or

• The power consumption of the system falls below 240 V*A (at

which time the OPDLY pin voltage is pulled to ground)

A 240 V*A fault event is detected at t240VA_F. At this time, the

FAULT signal transitions to the low state and the GATE pin is

pulled to ground. The FAULT signal is latched and the chip will

pull down the GATE voltage until the EN pin of the ACS760

transitions to the low state and then back to the high state.

As shown in the timing diagram, certain ACS760 signals (the

FAULT signal and the OPDLY pin voltage) are reset when the EN

pin transitions to the low state. These signals are reset in order to

guarantee normal device operation (soft start and fault monitor-

ing) when the EN signal transitions back to the high state.

0.4 V

0A

0V

3.3 V

1.83 V

22 A

VIOUT Voltage

Load Current / IP

GATE Voltage

FAULT

≈0 V

0V

0V

0V

0V

12 V

3.85 V threshold

EN

CG Pin Voltage

VLOAD to Load

OPDLY Pin Voltage

OCDLY Pin Voltage

12 V on IP+ Pins

tEN1

tINIT_F t240VA_F

0.4 V

5.5 V

tRESET

Figure 1. Timing Diagram for 240 V*A Fault

1.648 V

19.2 A

22 V

3.3 V

5.5 V

12 V

Time

Allegro MicroSystems, LLC

8

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

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