ADP3208C データシートの表示（PDF） - ON Semiconductor

部品番号

コンポーネント説明

メーカー

ADP3208C

7-Bit, Programmable, Dual-Phase, Mobile, CPU, Synchronous Buck Controller

ON Semiconductor 

ADP3208C

SPECIFICATIONS

VCC = PVCC1 = PVCC2 = BST1 = BST2 = high = 5 V, FBRTN = GND = SW1 = SW2 = PGND1 = PGND2 = low = 0 V, EN = VARFREQ =

high, DPRSLP = 0 V, PSI = 1.05 V, VVID = 1.2000 V, TA = -10°C to 100°C, unless otherwise noted.1 Current entering a pin (sunk by the

device) has a positive sign. RREF = 80 kΩ.

Table 1.

Parameter

VOLTAGE CONTROL

VOLTAGE ERROR AMPLIFIER

(VEAMP)

FB, LLINE Voltage Range2

FB, LLINE Offset Voltage2

FB, LLINE Bias Current2

LLINE Positioning Accuracy

COMP Voltage Range2

COMP Current

COMP Slew Rate

Symbol

VFB, VLLINE

VOSVEA

IFB

VFB − VVID

VCOMP

ICOMP

SRCOMP

Gain Bandwidth2

VID DAC VOLTAGE REFERENCE

VDAC Voltage Range3

VDAC Accuracy

GBW

VFB − VVID

VDAC Differential

Nonlinearity2

VDAC Line Regulation

VDAC Boot Voltage2

Soft-start Delay2

Soft-start Time

Boot Delay

VDAC Slew Rate

ΔVFB

VBOOTFB

tDSS

tSS

tBOOT

FBRTN Current

VOLTAGE MONITORING

and PROTECTION

POWER GOOD

CSREF Under-voltage

Threshold

CSREF Over-voltage

Threshold

IFBRTN

VUVCSREF

VOVCSREF

Conditions

Min Typ

Max Units

Relative to CSREF = VDAC

Relative to CSREF = VDAC

Measured on FB relative to VVID, LLINE forced 80 mV

below CSREF

Operating Range

COMP = 2 V, CSREF = VDAC

FB forced 200 mV below CSREF

FB forced 200 mV above CSREF

CCOMP = 10 pF, CSREF = VDAC, Open loop

configuration

FB forced 200 mV below CSREF

FB forced 200 mV above CSREF

Non-inverting unit gain configuration, RFB = 1 kΩ

−200

-0.5

−100

−78 −80

0.85

−0.75

6

15

−20

20

+200 mV

+0.5 mV

100 nA

−82 mV

4.0 V

mA

mA

V/μs

V/μs

MHz

See VID table

0

Measured on FB (includes offset), relative to VVID,

for VID table see Table 6

VVID = 1.2125V to 1.5000V

−9

VVID = 0.3000V to 1.2000V

−7.5

−1

1.5 V

+9 mV

+7.5 mV

+1 LSB

VCC = 4.75 V to 5.25 V

Measured during boot delay period

Measured from EN pos edge to FB = 50 mV

Measured from EN pos edge to FB settles to Vboot =

1.2 V within -5 %

Measured from FB settling to Vboot = 1.2 V within -5

% to CLKEN# neg edge

Soft-start

Non-LSB VID step, DPRSLP = H, Slow C4 Entry/Exit

Non-LSB VID step, DPRSLP = L, Fast C4 Exit

0.05

%

1.200

V

200

μs

1.7

ms

150

μs

0.0625

0.25

1

90

200

LSB/μs

LSB/μs

LSB/μs

μA

Relative to DAC voltage = 0.5 V to 1.5 V

Relative to DAC voltage = 0.3 V to 0.4875 V

Relative to nominal DAC voltage

Rev. 1 | Page 4 of 41 | www.onsemi.com

−360

−360

150

−300

−200

200

−240 mV

−160 mV

250 mV

Share Link: