ADP3208CJCPZ-RL データシートの表示（PDF） - ON Semiconductor
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ADP3208CJCPZ-RL
ON Semiconductor
ADP3208CJCPZ-RL Datasheet PDF : 41 Pages
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ADP3208C
Parameter
PULSE WIDTH
MODULATOR
CLOCK OSCILLATOR
RT Voltage
PWM Clock Frequency
Range2
PWM Clock Frequency
Symbol
VRT
fCLK
fCLK
RAMP GENERATOR
RAMP Voltage
RAMP Current Range2
PWM COMPARATOR
PWM Comparator Offset2
RPM COMPARATOR
RPM Current
RPM Comparator Offset2
EPWM CLOCK SYNC
Trigger Threshold2
VRAMP
IRAMP
VOSRPM
IRPM
VOSRPM
SWITCH AMPLIFIER
SW Common Mode Range2
SW Resistance
ZERO CURRENT SWITCHING
COMPARATOR
SW ZCS Threshold
Masked Off-Time
SYSTEM I/O BUFFERS
VID[6:0], PSI# INPUTS
Input Voltage
VSW(X)CM
RSW_PGND(X)
VDCM(SW1)
tOFFMSKD
Input Current
VID Delay Time2
DPRSLP
Input Voltage
Input Current
Conditions
Min Typ
Max Units
VARFREQ = high, RT = 125 kΩ, VVID = 1.5000 V
VARFREQ = low
See also VRT(VVID) formula
Operating Range
TA = +25°C, VVID = 1.2000 V
RT = 73 kΩ
RT = 125 kΩ
RT = 180 kΩ
EN = high, IRAMP = 30 μA
EN = low
EN = high
EN = low, RAMP = 19 V
VRAMP − VCOMP
VVID = 1.2 V, RT = 125 kΩ, VARFREQ = High
See also IRPM(RT) formula
VCOMP − (1 +VRPM)
Relative to COMP sampled TCLK earlier
2-phase configuration
1-phase configuration
Operating Range for current sensing
Measured from SW to PGND
1.22 1.25
0.98 1
0.3
1.27 V
1.02 V
3
MHz
970 1270
705 830
500 600
1570 kHz
955 kHz
700 kHz
0.9 1
VIN
1
−0.5
1.1 V
V
100 μA
+0.5 μA
−3
3
mV
−8.8
μA
−3
3
mV
400
450
−600
3
mV
mV
+200 mV
kΩ
DCM mode, DPRSLP = 3.3 V
−6
mV
Measured from DRVH neg edge to DRVH pos edge
700
ns
at max frequency of operation
Refers to driving signal level
Logic low, Isink ≥ 1 μA
Logic high, Isource ≤ −5 μA
V = 0.2 V
VID[6:0], DPRSLP (active pull down to GND)
PSI# (active pull-up to VCC)
Any VID edge to FB change 10%
Refers to driving signal level
Logic low, Isink > 1 μA
Logic high, Isource < -5 μA
DPRSLP = low
DPRSLP = high
Rev. 1 | Page 6 of 41 | www.onsemi.com
0.7
−1
+1
200
0.3 V
V
μA
μA
ns
2.3
−1
+2
1.0 V
V
μA
μA
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