AK5351 データシートの表示（PDF） - Asahi Kasei Microdevices

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AK5351

Enhanced Dual bit ∆Σ 20bit ADC

Asahi Kasei Microdevices 

ASAHI KASEI

No.

1

2

3

Pin Name

AINR+

AINR-

VREF

4

VA

5

AGND

6

AINL+

7

AINL-

8

TST1

10

TST2

11

TST3

14

TST4

9

HPFE

12

VD

13

DGND

16

PD

17

MCLK

18

SCLK

19

LRCK

20

FSYNC

[AK5351]

PIN/FUNCTION

I/O

FUNCTION

I Right channel analog positive input pin

I Right channel analog negative input pin

O Voltage Reference output pin

(VA-2.6V)

Normally connected to VA with a 0.1uF ceramic capacitor in

parallel with a 10uF electrolytic capacitor.

- Analog section Analog Power Supply, +5V

- Analog section Analog Ground

I Left channel analog positive input pin

I Left channel analog negative input pin

Test pin

(Pull-down pin)

Should be left floating.

I High Pass Filter Enable pin

(Pull-up pin)

"H": ON

"L": OFF

- Digital section Digital Power Supply pin, +5V

- Digital section Digital Ground pin

I Power Down pin

"L" brings the device into power-down mode. Must be done

once after power-on.

I Master Clock input pin

CMODE="H":384fs

CMODE="L":256fs

I/O Serial Data Clock pin

Data is clocked out at the falling edge of SCLK.

Slave mode: 64fs clock is input usually.

Master mode: SCLK outputs a 64fs clock.

SCLK stays low during the power-down mode(PD="L").

I/O L/R Channel Clock Select pin

Slave mode: An fs clock is fed to this LRCK pin.

Master mode: LRCK output an fs clock.

LRCK goes "H" at SMODE2="L" and "L" at SMODE2="H"

during reset when SMODE1 "H".

I/O Frame Synchronization Signal pin

Slave mode: When "H", data bits are clocked out on SDATA.

As I2S slave mode ignores FSYNC, it should hold "L" or

"H".

Master mode: FSYNC outputs 2fs clock.

Stay low during the power-down mode(PD="L").

0166-E-00

-3-

1997/4

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