AL1402 データシートの表示（PDF） - Unspecified
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AL1402 Datasheet PDF : 8 Pages
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Table 1 Electrical Characteristics and Operating Conditions
Symbol
Description
Min
Typ
Max Units
Recommended Operating Conditions
VDD
Supply Voltage
4.5
5.0
5.5
V
IDD Master Supply Current, Master
-
7.7
-
mA
IDD Slave
Supply Current, Slave
-
5.4
-
mA
GND
Ground
-
0.0
-
V
Fs
Sample rate
30
48
55
kHz
Temp
Temperature
0
25
70
°C
Inputs (WDCLK, FMT, OPDIGIN, MODE, LINMODE, MUTE, HOLDERR)
VIH
Logical “1” input voltage
0.75 VDD
-
-
VDD
VIL
Logical “0” input voltage
-
-
0.25 VDD
VDD
IIH
Logical “1” input current
-
-
1
uA
IIL
Logical “0” input current
-
-
1
uA
CIN
Logic Input Capacitance
-
5
-
pF
Outputs (WDCLK, DVCO, OPDIGTHRU, SVCO, BCLK, ERROR)
VOH
Logical “1” output voltage
0.9 VDD
-
-
VDD
VOL
Logical “0” output voltage
-
-
0.1 VDD
VDD
IOH
Logical “1” output current
-
-
-8
mA
IOL
Logical “0” output current
-
-
8
mA
Outputs (OUT, USER)
VOH
Logical “1” output voltage
0.9 VDD
-
-
VDD
VOL
Logical “0” output voltage
-
-
0.1 VDD
VDD
IOH
Logical “1” output current
-
-
-2
mA
IOL
Logical “0” output current
-
-
2
mA
Table 2 Pin Descriptions
Pin # Name
Pin
Description
Type
1
GND
Power Ground pin
2
MODE0
Input Mode select
3
FMT0
Input Format select
4
FMT1
Input Format select
5
MODE1
Input Mode select
6
OPDIGIN
Input Input from optical receiver
7
SVCO
Output
Derived clock from WDCLK in slave mode; derived from DVCO in Master mode
(nominal 12.288MHz, 256x Fs)
8
WDCLK
I/O Input or output word clock, see Table 4, Modes (nominal 48KHz, Fs)
9
BCLK
Output Bit clock (nominal 3.072MHz, 64 x Fs)
10
OUT 1/2
Output Channels 1 and 2 data output
11
OUT 3/4
Output Channels 3 and 4 data output
12
OUT 5/6
Output Channels 5 and 6 data output
13
OUT 7/8
Output Channels 7 and 8 data output
14
USER0
Output USER0 data bit output. Used to receive timecode
15
USER1
Output USER1 data bit output. Used to receive MIDI data.
16
USER2
Output USER2 data bit output. Reserved.
17
USER3
Output USER3 data bit output. Reserved.
18
DVCO
Output Recovered clock from data stream(nominal 12.288MHz, 256 x Fs)
19
OPDIGTHRU Output OPDIGIN is regenerated and clocked out on this pin to allow daisy-chaining
20
HOLDERR
Input
If high, the ERROR pin stays high until the cause of the error is removed AND
the HOLDERR pin goes low.
21
ERROR
Output
Indicates lack of input or failure to synchronize to data stream, mutes data
outputs but not clock outputs
22
MUTE
Input If high, mutes outputs
23
LINMODE
Input Tie high
24
VDD
Power +5V power pin
Alesis Semiconductor
DS1402-0702
12555 Jefferson Blvd., Suite 285
Los Angeles, CA 90066
Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
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