AM29F800BT-90DTC1 データシートの表示（PDF） - Advanced Micro Devices

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AM29F800BT-90DTC1

8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 5.0 Volt-only, Boot Sector Flash Memory—Die Revision 1

Advanced Micro Devices 

SUPPLEMENT

GENERAL DESCRIPTION

The Am29F800B in Known Good Die (KGD) form is a

8 Mbit, 5.0 volt-only Flash memory. AMD defines KGD

as standard product in die form, tested for functionality

and speed. AMD KGD products have the same relia-

bility and quality as AMD products in packaged form.

Am29F800B Features

The Am29F800B is an 8 Mbit, 5.0 volt-only Flash

memory organized as 1,048,576 bytes or 524,288

words. The word-wide data (x16) appears on

DQ15–DQ0; the byte-wide (x8) data appears on

DQ7–DQ0. This device is designed to be programmed

in-system with the standard system 5.0 volt VCC

supply. A 12.0 V VPP is not required for write or erase

operations. The device can also be programmed in

standard EPROM programmers.

This device is manufactured using AMD’s 0.35 µm

process technology, and offers all the features and ben-

efits of the Am29F800, which was manufactured using

0.5 µm process technology.

To eliminate bus contention the device has separate

chip enable (CE#), write enable (WE#) and output

enable (OE#) controls.

The device requires only a single 5.0 volt power sup-

ply for both read and write functions. Internally gener-

ated and regulated voltages are provided for the

program and erase operations.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state-machine that

controls the erase and programming circuitry. Write

cycles also internally latch addresses and data needed

for the programming and erase operations. Reading

data out of the device is similar to reading from other

Flash or EPROM devices.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin.

Device erasure occurs by executing the erase com-

mand sequence. This initiates the Embedded Erase

algorithm—an internal algorithm that automatically

preprograms the array (if it is not already programmed)

before executing the erase operation. During erase, the

device automatically times the erase pulse widths and

verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

(toggle) status bits. After a program or erase cycle has

been completed, the device is ready to read array data

or accept another command.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low

VCC detector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achieved via programming equipment.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to the

system reset circuitry. A system reset would thus also

reset the device, enabling the system microprocessor

to read the boot-up firmware from the Flash memory.

The system can place the device into the standby

mode. Power consumption is greatly reduced in

this mode.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

h igh est level s of q ual ity, re lia bil ity an d cost

effectiveness. The device electrically erases all

bits within a sector simultaneously via

F o w l e r -N o r d h e i m t u n n e l i n g . T h e d a t a i s

programmed using hot electron injection.

ELECTRICAL SPECIFICATIONS

Refer to the Am29F800B data sheet, PID 21504, for full

electrical specifications on the Am29F800B in KGD

form.

2

Am29F800B Known Good Die

5/4/98

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