AT25128-10PI-1.8 データシートの表示（PDF） - Atmel Corporation

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AT25128-10PI-1.8

SPI Serial EEPROMs

Atmel Corporation 

0872O–SEEPR–03/05

AT25128/256

WRITE ENABLE (WREN): The device will power-up in the write disable state when VCC

is applied. All programming instructions must therefore be preceded by a Write Enable

instruction.

WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write

Disable instruction disables all programming modes. The WRDI instruction is indepen-

dent of the status of the WP pin.

READ STATUS REGISTER (RDSR): The Read Status Register instruction provides

access to the status register. The Ready/Busy and Write Enable status of the device

can be determined by the RDSR instruction. Similarly, the Block Write Protection bits

indicate the extent of protection employed. These bits are set by using the WRSR instruc-

tion.

Table 6. Status Register Format

Bit 7

Bit 6

Bit 5

WPEN

X

X

Bit 4

X

Bit 3

BP1

Bit 2

BP0

Bit 1

WEN

Bit 0

RDY

Table 7. Read Status Register Bit Definition

Bit

Definition

Bit 0 (RDY)

Bit 0 = “0” (RDY) indicates the device is READY.

Bit 0 = “1” indicates the write cycle is in progress.

Bit 1 (WEN)

Bit 1 = “0” indicates the device is not WRITE ENABLED. Bit 1 = 1

indicates the device is WRITE ENABLED.

Bit 2 (BP0)

See Table 8.

Bit 3 (BP1)

See Table 8.

Bits 4 - 6 are “0”s when device is not in an internal write cycle.

Bit 7 (WPEN)

See Table 9.

Bits 0 – 7 are “1”s during an internal write cycle.

WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select

one of four levels of protection. The AT25128/256 is divided into four array segments.

Top quarter (1/4), top half (1/2), or all of the memory segments can be protected. Any of

the data within any selected segment will therefore be READ only. The block write pro-

tection levels and corresponding status register control bits are shown in Table 8.

The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties

and functions as the regular memory cells (e.g. WREN, tWC, RDSR).

Table 8. Block Write Protect Bits

Status Register Bits

Array Addresses Protected

Level

BP1

BP0

AT25128

AT25256

0

0

0

None

None

1(1/4)

0

1

3000 - 3FFF

6000 - 7FFF

2(1/2)

1

0

2000 - 3FFF

4000 - 7FFF

3(All)

1

1

0000 - 3FFF

0000 - 7FFF

7

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