CD4029BMS データシートの表示（PDF） - Intersil

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CD4029BMS

CMOS Presettable Up/Down Counter

Intersil 

Timing Diagrams (Continued)

UP/DOWN

PRESET

ENABLE

CD4029BMS

“RIPPLE CLOCKING”

UP/D PE J1 J2 J3 J4

CI

CD4029

CO

B/D CL Q1 Q2 Q3 Q4

UP/D PE J1 J2 J3 J4

CI

CD4029

CO

B/D CL Q1 Q2 Q3 Q4

UP/D PE J1 J2 J3 J4

CI

CD4029

CO

B/D CL Q1 Q2 Q3 Q4

CLOCK

BINARY/

DECADE

1/4 CD4071B

1/4 CD4071B

RIPPLE CLOCKING MODE:

THE UP/DOWN CONTROL CAN BE CHANGED AT ANY COUNT. THE ONLY

RESTRICTION ON CHANGING THE UP/DOWN CONTROL IS THAT THE CLOCK

INPUT TO THE FIRST COUNTING STAGE MUST BE HIGH. FOR CASCADING

COUNTERS OPERATING IN A FIXED UP-COUNT OR DOWN-COUNT MODE,

THE OR GATES ARE NOT REQUIRED BETWEEN STAGES, AND CO IS CON-

NECTED DIRECTLY TO THE CL INPUT OF THE NEXT STAGE WITH CI

GROUNDED.

FIGURE 13. CASCADING COUNTER PACKAGES (Continued)

Chip Dimensions and Pad Layout

Dimensions in parentheses are in millimeters

and are derived from the basic inch dimensions

as indicated. Grid graduations are in mils (10-3 inch)

METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.

PASSIVATION: 10.4kÅ - 15.6kÅ, Silane

BOND PADS: 0.004 inches X 0.004 inches MIN

DIE THICKNESS: 0.0198 inches - 0.0218 inches

7-808

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