CDB53L32A データシートの表示（PDF） - Cirrus Logic
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CDB53L32A Datasheet PDF : 38 Pages
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CS53L32A
SWITCHING CHARACTERISTICS (TA = -10 to 70° C; VA = 1.7 V - 3.6 V; Inputs: Logic 0 = GND,
Logic 1 = VL, CL = 20 pF)
Parameters
Symbol
Min
Typ Max Units
Input Sample Rate
MCLK Pulse Width High
Base Rate Mode Fs
High Rate Mode Fs
MCLK/LRCK = 1024
2
-
50
kHz
50
-
100
kHz
8
-
-
ns
MCLK Pulse Width Low
MCLK/LRCK = 1024
8
-
-
ns
MCLK Pulse Width High
MCLK/LRCK = 768
10
-
-
ns
MCLK Pulse Width Low
MCLK/LRCK = 768
10
-
-
ns
MCLK Pulse Width High
MCLK/LRCK = 512
15
-
-
ns
MCLK Pulse Width Low
MCLK/LRCK = 512
15
-
-
ns
MCLK Pulse Width High MCLK / LRCK = 384 or 192
21
-
-
ns
MCLK Pulse Width Low MCLK / LRCK = 384 or 192
21
-
-
ns
MCLK Pulse Width High MCLK / LRCK = 256 or 128
31
-
-
ns
MCLK Pulse Width Low MCLK / LRCK = 256 or 128
Master Mode
31
-
-
ns
SCLK Falling to LRCK Edge
SCLK Falling to SDATA Valid
SCLK Duty Cycle
tslrd
-20
-
20
ns
tsdo
0
-
20
ns
40
50
60
%
Slave Mode
LRCK Duty Cycle
40
50
60
%
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period
Base Rate Mode
High Rate Mode
tsclkl
tsclkh
tsclkw
tsclkw
20
20
----------1-----------
( 128 )F s
(---6---4--1--)--F----s--
-
-
ns
-
-
ns
-
-
ns
-
-
ns
SCLK Falling to LRCK Edge
SCLK Falling to SDATA Valid
tslrd
Base Rate Mode tdss
High Rate Mode tdss
-20
-
20
ns
-
-
1
ns
(512)Fs
-
-
1
ns
(256)Fs
DS513PP1
9
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