CS61535A データシートの表示（PDF） - Cirrus Logic
部品番号
コンポーネント説明
メーカー
CS61535A Datasheet PDF : 48 Pages
| |||
CS61535A
T1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Symbol Min
Typ
Max Units
Crystal Frequency
ACLKI Duty Cycle
ACLKI Frequency
RCLK Duty Cycle
(Note 29)
(Note 30)
(Notes 31, 32)
fc
tpwh3/tpw3
faclki
tpwh1/tpw1
-
6.176000 -
MHz
40
-
60
%
-
1.544
-
MHz
-
78
-
%
-
29
-
%
RCLK Cycle Width
(Note 32)
Rise Time, All Digital Outputs
(Note 33)
Fall Time, All Digital Outputs
(Note 33)
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
RPOS/RNEG Valid Before RCLK Falling
(Note 34)
RDATA Valid Before RCLK Falling
(Note 35)
RPOS/RNEG Valid Before RCLK Rising
(Note 31)
RPOS/RNEG Valid After RCLK Falling
(Note 34)
RDATA Valid After RCLK Falling
(Note 35)
RPOS/RNEG Valid After RCLK Rising
(Note 31)
TCLK Frequency
TCLK Pulse Width
(Notes 12, 31, 34, 36, 37)
(Notes 35, 36, 37)
tpw1
tpwh1
tpwl1
tr
tf
tsu2
th2
tsu1
tsu1
tsu1
th1
th1
th1
ftclk
tpwh2
320
648
980 ns
130
190
240 ns
100
458
850 ns
-
-
85
ns
-
-
85
ns
25
-
-
ns
25
-
-
ns
150
274
-
ns
150
274
-
ns
150
274
-
ns
150
274
-
ns
150
274
-
ns
150
274
-
ns
-
1.544
-
MHz
80
-
500 ns
150
-
500 ns
Notes: 29. Crystal must meet specifications described in CXT6176/CXT8192 data sheet.
30. ACLKI provided by an external source or TCLK, but not RCLK.
31. Hardware Mode, or Host Mode (CLKE = 0).
32. RCLK cycle width will vary with extent by which pulses displaced by jitter. Specified under worst case
jitter conditions: 0.4 UI AMI data displacement for T1 and 0.2 UI AMI data displacement for E1.
33. At max load of 1.6 mA and 50 pF.
34. Host Mode (CLKE = 1).
35. Extended Hardware Mode.
36. The maximum TCLK burst rate is 5 MHz and tpw2(min) = 200 ns. The maximum gap size that can
be tolerated on TCLK is 12 VI.
37. The transmitted pulse width does not depend on the TCLK duty cycle.
RCLK
tpw1
tpwl1
tpwh1
EXTENDED
HARDWARE
MODE OR
HOST MODE
(CLKE = 1)
RPOS
RNEG
RDATA
BPV
RCLK
t su1
t h1
HARDWARE
MODE OR
HOST MODE
(CLKE = 0)
Figure 1. Recovered Clock and Data Switching Characteristics
6
DS40F2
Share Link: 