CY7B9911V データシートの表示（PDF） - Cypress Semiconductor

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CY7B9911V

High Speed Low Voltage Programmable Skew Clock Buffer

Cypress Semiconductor 

CY7B9911V

3.3V RoboClock+™

frequency, while still maintaining the low skew characteristics of

the clock driver. The LVPSCB performs all of the functions

described in this section at the same time. It can multiply by two

and four or divide by two (and four) at the same time. This shifts

its outputs over a wide range or maintain zero skew between

selected outputs.

Figure 7. Multi-Function Clock Driver

27.5 MHz

DISTRIBUTION

CLOCK

REF

FB

REF

FS

4F0

4Q0

4F1

4Q1

3F0

3Q0

3F1

3Q1

2F0

2Q0

2F1

2Q1

1F0

1Q0

1F1

1Q1

TEST

Z0

110 MHz

INVERTED

27.5 MHz Z0

110 MHz

ZERO SKEW Z0

LOAD

LOAD

LOAD

110 MHz

SKEWED –2.273 ns (–4tU) Z0

LOAD

Figure 8. Board-to-Board Clock Distribution

SYSTEM

CLOCK

REF

FB

REF

FS

4F0

4Q0

4F1

4Q1

3F0

3Q0

3F1

3Q1

2F0

2Q0

2F1

2Q1

1F0

1Q0

1F1

1Q1

TEST

L1

L2

LOAD

Z0

LOAD

Z0

L3

L4

Z0

Z0

FB

REF

FS

4F0

4F1

4Q0

4Q1

3F0 3Q0

3F1 3Q1

2F0 2Q0

2F1 2Q1

1F0 1Q0

1F1 1Q1

TEST

LOAD

LOAD

LOAD

Figure 8 shows the CY7B9911V connected in series to construct a zero skew clock distribution tree between boards. Delays of the

downstream clock buffers are programmed to compensate for the wire length (that is, select negative skew equal to the wire delay)

necessary to connect them to the master clock source, approximating a zero delay clock tree. Cascaded clock buffers accumulates

low frequency jitter because of the non-ideal filtering characteristics of the PLL filter. Do not connect more than two clock buffers in a

series.

Document Number: 38-07408 Rev. *D

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