CY3682(2004) データシートの表示（PDF） - Cypress Semiconductor
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CY3682 Datasheet PDF : 42 Pages
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FO R
FO R
CY7C68001
11.3.3 Slave FIFO Synchronous Packet End Strobe
IFCLK
PKTEND
tSPE
tPEH
FLAGS
tXFLG
Figure 11-7. Slave FIFO Synchronous Packet End Strobe Timing Diagram[12]
Table 11-11. Slave FIFO Synchronous Packet End Strobe Parameters, Internally Sourced IFCLK[13]
Parameter
Description
Min.
Max.
tIFCLK
tSPE
tPEH
tXFLG
IFCLK Period
PKTEND to Clock Set-up Time
Clock to PKTEND Hold Time
Clock to FLAGS Output Propagation Delay
20.83
14.6
0
9.5
Table 11-12. Slave FIFO Synchronous Packet End Strobe Parameters, Externally Sourced IFCLK[13]
Parameter
tIFCLK
tSPE
tPEH
tXFLG
Description
IFCLK Period
PKTEND to Clock Set-up Time
Clock to PKTEND Hold Time
Clock to FLAGS Output Propagation Delay
Min.
20
8.6
2.5
Max.
200
13.5
11.3.4 Slave FIFO Synchronous Address
IFCLK
SLCS#/FIFOADR[2:0]
tSFA
tFAH
Figure 11-8. Slave FIFO Synchronous Address Timing Diagram
Table 11-13. Slave FIFO Synchronous Address Parameters[13]
Parameter
Description
tIFCLK
tSFA
tFAH
Interface Clock Period
FIFOADR[2:0] to Clock Set-up Time
Clock to FIFOADR[2:0] Hold Time
Min.
20
25
10
Max.
200
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
ns
Unit
ns
ns
ns
Document #: 38-08013 Rev. *E
Page 28 of 42
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