CY7C68001(2004) データシートの表示（PDF） - Cypress Semiconductor
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CY7C68001 Datasheet PDF : 42 Pages
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FO R
FO R
CY7C68001
11.3.5 Slave FIFO Asynchronous Read
SLRD
FLAGS
tRDpwl
tXFD
tRDpwh
tXFLG
DATA
SLOE
N
tOEon
N+1
tOEoff
Figure 11-9. Slave FIFO Asynchronous Read Timing Diagram[12]
Table 11-14. Slave FIFO Asynchronous Read Parameters[14]
Parameter
tRDpwl
tRDpwh
tXFLG
tXFD
tOEon
tOEoff
Description
SLRD Pulse Width Low
SLRD Pulse Width HIGH
SLRD to FLAGS Output Propagation Delay
SLRD to FIFO Data Output Propagation Delay
SLOE Turn-on to FIFO Data Valid
SLOE Turn-off to FIFO Data Hold
11.3.6 Slave FIFO Asynchronous Write
SLWR/SLCS#
DATA
tWRpwl
tWRpwh
tSFD
tFDH
FLAGS
tXFD
Min.
50
50
Max.
70
15
10.5
10.5
Figure 11-10. Slave FIFO Asynchronous Write Timing Diagram[12]
Table 11-15. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK[14]
Parameter
Description
tWRpwl
SLWR Pulse LOW
tWRpwh
SLWR Pulse HIGH
tSFD
SLWR to FIFO DATA Set-up Time
tFDH
FIFO DATA to SLWR Hold Time
tXFD
SLWR to FLAGS Output Propagation Delay
Note:
14. Slave FIFO asynchronous parameter values are using internal IFCLK setting at 48 MHz.
Min.
50
70
10
10
Max.
70
Unit
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
Document #: 38-08013 Rev. *E
Page 29 of 42
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