µPD78044H, 78045H, 78046H
5.2 CLOCK GENERATOR CIRCUIT
The clock generator circuit has two kinds of generator circuits: the main system clock and subsystem clock.
The instruction time can be changed.
• 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs (with main system clock: 5.0 MHz)
• 122 µs (with subsystem clock: 32.768 kHz)
Fig. 5-1 Clock Generator Circuit Block Diagram
XT1/P04
XT2
Subsystem
fXT
clock generator
circuit
Clock output circuit
Noise
fX
eliminator
8
fX
16
X1
Main system
clock generator
X2
circuit
fX
Pre-scaler
fX fX fX fX
2 22 23 24
STOP
Watch timer
1
2
fXT
2
Pre-scaler
Clock to
hardware peripherals
Standby
control
circuit
CPU clock (fCPU)
To INTP0
sampling clock
5.3 TIMER/EVENT COUNTER
Five channels of timer/event counters are provided.
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 2 channels
• Watch timer
: 1 channel
• Watchdog timer
: 1 channel
Table 5-2 Timer/Event Counter Groups and Configurations
Interval timer
External event counter
Timer output
PWM output
Pulse width measurement
Square wave output
Interrupt request
Test input
16-bit timer/
event counter
1 channel
1 channel
1 output
1 output
1 input
1 output
1
—
8-bit timer/
event counter
2 channels
—
2 outputs
—
—
2 outputs
2
—
Watch
timer
1 channel
—
—
—
—
—
1
1 input
Watchdog
timer
1 channel
—
—
—
—
—
1
—
17