DM96S02MX データシートの表示（PDF） - Fairchild Semiconductor
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DM96S02MX Datasheet PDF : 7 Pages
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Operation Notes
TIMING
1. An external resistor (RX) and an external capacitor (CX)
are required as shown in the Logic Diagram. The value
of RX may vary from 1.0 kΩ to 2.0 MΩ (DM96S02).
2. The value of CX may vary from 0 to any necessary
value available. If however, the capacitor has signifi-
cant leakage relative to VCC/RX the timing equations
may not represent the pulse width obtained.
3. Polarized capacitors may be used directly. The (+) ter-
minal of a polarized capacitor is connected to pin 1(15),
the (−) terminal to pin 2(14) and RX. Pin 1(15) will
remain positive with respect to pin 2(14) during the tim-
ing cycle. However, during quiescent (non-triggered)
conditions, pin 1(15) may go negative with respect to
pin 2(14) depending on values of RX and VCC. for val-
ues of RX ≥ 10 kΩ the maximum amount of capacitor
reverse polarity, pin 1(15) negative with respect to pin
2(14) is 500 mV. Most tantalum electrolytic capacitors
are rated for safe reverse bias operation up to 5% of
their working forward voltage rating; therefore, capaci-
tors having a rating of 10 WVdc or higher should be
used with the DM96S02 when RX ≥ 10 kΩ.
4. The output pulse width tW for RX ≥ 10 kΩ and CX ≥
1000 pF is determined as follows:
tW = 0.55 RXCX
Where RX is in kΩ, CX is in pF, t is in ns or RTX is in kΩ,
CX is in µF, t is in ms.
5. The output pulse width for RX < 10 kΩ or CX < 1000 pF
should be determined from pulse width versus CX or
RX graphs.
6. To obtain variable pulse width by remote trimming, the
following circuit is recommended:
7. Under any operating condition, CX and RX (Min) must
be kept as close to the circuit as possible to minimize
stray capacitance and reduce noise pickup.
8. VCC and ground wiring should conform to good high
frequency standards so that switching transients on
VCC and ground leads do not cause interaction
between one shots. Use of a 0.01 µF to 0.1µF bypass
capacitor between VCC and ground located near the
circuit is recommended.
TRIGGERING
1. The minimum negative pulse width into I0 is 8.0 ns; the
minimum positive pulse width into I1 is 12 ns.
2. Input signals to the DM96S02 exhibiting slow or noisy
transitions should use the positive trigger input I1 which
contains a Schmitt trigger.
3. When non-retriggerable operation is required, i.e.,
when input triggers are to be ignored during quasi-sta-
ble state, input latching is used to inhibit retriggering.
4. An overriding active LOW level direct clear is provided
on each multivibrator. By applying a LOW to the clear,
any timing cycle can be terminated or any new cycle
inhibited until the LOW reset input is removed. Trigger
inputs will not produce spikes in the output when the
reset is held LOW. A LOW-to-HIGH transition on CD
will not trigger the DM96S02. If the CD input goes HIGH
coincident with a trigger transition, the circuit will
respond to the trigger.
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