TMXF84622 データシートの表示（PDF） - Agere -> LSI Corporation
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TMXF84622 Datasheet PDF : 62 Pages
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TMXF84622 155 Mbits/s/622 Mbits/s Interface
SONET/SDH x84/x63 Ultramapper
Advance Data Sheet, Rev. 2
July 2001
Features (continued)
s LOF detection, OOF detection, REI monitoring, RDI
monitoring, and B2 error detection is performed on
the three serial 155 Mbits/s data inputs from the CDR
receive blocks.
s REI and RDI are generated from the received data
and sent to the transmit side for insertion in the trans-
mitted serial 155 Mbits/s data.
s B2 is calculated and inserted in the transmitted serial
data. B2 error insertion is allowed.
TMUX Features
s Multiplexes twelve STS-1 signals or four STS-3c sig-
nals into a SONET STS-12 signal.
s Multiplexes three STS-1 signals into a SONET
STS-3 signal.
s Multiplexes four STM-1 (AU-4 or 3xAU-3) signals into
an SDH STM-4 signal.
s Multiplexes three VC-3 signals into an SDH STM-1
(3xAU-3) signal.
s Multiplexes three VC-3 signals into an SDH STM-1
(AU-4) signal via a TUG-3 construction.
s Demultiplexes twelve STS-1 signals or four STS-3c
signals from a SONET STS-12 signal.
s Demultiplexes three STS-1 signals from a SONET
STS-3 signal.
s Demultiplexes four STM-1 (AU-4 or 3xAU-3) signals
from an SDH STM-4.
s Demultiplexes three VC-3 signals from an SDH STM-
1 (3xAU-3) signal.
s Demultiplexes three VC-3 signals from an SDH STM-
1 (AU-4) signal via a TUG-3 deconstruction.
s Provides STS1-only mode for receive and transmit
directions.
s Provides complete functionality for SDH MSP 1 + 1
protection switching.
s Provides SONET/SDH loss-of-signal (LOS), out-of-
frame (OOF) and loss-of-frame (LOF) detection.
s Provides STS-12/STM-4/STS-3/STM-1/STS1 select-
able scrambler/descrambler functions.
s Provides STS-12/STM-4/STS-3/STM-1/STS1 B1/B2/
B3 generation/detection.
s Provides STS-12/STM-1/STS-3/STM-1/STS1/
pointer interpretation.
s Complies with GR-253-CORE, T1.105, G.707,
G.783, G.806, G.821, and ETSI 417-1-1.
VT/TU Features
s Maps T1/E1/J1 into VT/TU structures:
— T1 into VT1.5/TU-11/TU-12.
— J1 into VT1.5/TU-11/TU-12.
— E1 into VT2/TU-12.
s Maps VC-11/VC-12 into VTG/TUG-2 structures:
— VC-11 into VT1.5/TU-11/TU-12/VTG/TUG-2.
— VC-12 into VT2/TU-12/VTG/TUG-2.
s Supports asynchronous, byte synchronous, and bit
synchronous mappings.
s Supports automatic generation or microprocessor
overwrite of one bit RDI-V and one bit RFI-V.
s Supports automatic generation or microprocessor
overwrite of enhanced RDI-V.
s Supports ADM applications with tributary loopback
and tributary pointer processing.
s Supports unidirectional path switch ring (UPSR)
applications with a low-order path overhead access
channel.
s Supports TIM-V generation and termination for all
28/21 VT/TU signals.
s Supports BIP-V BER insertion and detection.
s Supports fast AIS generation for downstream
devices.
s Supports one second error counters for BIP-V and
REI-V.
s Complies with GR-253-CORE, G.707, T1.105,
G.704, G.783, JT-G707, GR-499, ETS 300 417-1-1.
Test Pattern Generator Features
s Configurable test pattern generator: DS1, E1, DS2,
E3, DS3, and STS1 formats.
s Pseudorandom bit sequence (PRBS, also known as
pseudonoise or PN sequences) based on maximal-
length feedback shift register sequences; PN codes
selectable from the following options: QRSS,
PRBS15, PRBS20, PRBS23, ALT_01, ALL_ONES,
USER pattern (16 bits, repeating).
s The test pattern can be transmitted either unframed
or as the payload of a framed signal as defined in
ITU-T.
s Single bit errors or framing errors may be injected
into any test pattern, under register control.
s Any sink or receiving channel may be replaced by a
test pattern monitor, which can detect and count bit
errors or misconfigurations, and/or detect idle condi-
tions or AIS.
6
Agere Systems Inc.
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