FS6370 データシートの表示（PDF） - Unspecified

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FS6370

EEPROM Programmable 3-PLL Clock Generator IC

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FS6370-01

EEPROM Programmable 3-PLL Clock Generator IC

8.2.2 Random Register Write Procedure

Random write operations allow the master to directly

write to any register. To initiate a write procedure, the

R/W bit that is transmitted after the seven-bit device ad-

dress is a logic-low. This indicates to the addressed slave

device that a register address will follow after the slave

device acknowledges its device address. The register

address is written into the slave’s address pointer. Fol-

lowing an acknowledge by the slave, the master is al-

lowed to write eight bits of data into the addressed regis-

ter. A final acknowledge is returned by the device, and

the master generates a STOP condition.

If either a STOP or a repeated START condition occurs

during a Register Write, the data that has been trans-

ferred is ignored.

To initiate a write procedure, the R/W bit that is transmit-

ted after the seven-bit device address is a logic-low. This

indicates to the addressed slave device that a register

address will follow after the slave device acknowledges

its device address. The register address is written into the

slave’s address pointer. Following an acknowledge by the

slave, the master is allowed to write up to sixteen bytes of

data into the addressed register before the register ad-

dress pointer overflows back to the beginning address.

An acknowledge by the device between each byte of data

must occur before the next data byte is sent.

Registers are updated every time the device sends an

acknowledge to the host. The register update does not

wait for the STOP condition to occur. Registers are

therefore updated at different times during a Sequential

Register Write.

8.2.3 Random Register Read Procedure

Random read operations allow the master to directly read

from any register. To perform a read procedure, the R/W

bit that is transmitted after the seven-bit address is a

logic-low, as in the Register Write procedure. This indi-

cates to the addressed slave device that a register ad-

dress will follow after the slave device acknowledges its

device address. The register address is then written into

the slave’s address pointer.

Following an acknowledge by the slave, the master gen-

erates a repeated START condition. The repeated

START terminates the write procedure, but not until after

the slave’s address pointer is set. The slave address is

then resent, with the R/W bit set this time to a logic-high,

indicating to the slave that data will be read. The slave

will acknowledge the device address, and then transmits

the eight-bit word. The master does not acknowledge the

transfer but does generate a STOP condition.

8.2.4 Sequential Register Write Procedure

Sequential write operations allow the master to write to

each register in order. The register pointer is automati-

cally incremented after each write. This procedure is

more efficient than the Random Register Write if several

registers must be written.

8.2.5 Sequential Register Read Procedure

Sequential read operations allow the master to read from

each register in order. The register pointer is automati-

cally incremented by one after each read. This procedure

is more efficient than the Random Register Read if sev-

eral registers must be read.

To perform a read procedure, the R/W bit that is trans-

mitted after the seven-bit address is a logic-low, as in the

Register Write procedure. This indicates to the addressed

slave device that a register address will follow after the

slave device acknowledges its device address. The reg-

ister address is then written into the slave’s address

pointer.

Following an acknowledge by the slave, the master gen-

erates a repeated START condition. The repeated

START terminates the write procedure, but not until after

the slave’s address pointer is set. The slave address is

then resent, with the R/W bit set this time to a logic-high,

indicating to the slave that data will be read. The slave

will acknowledge the device address, and then transmits

all sixteen bytes of data starting with the initial addressed

register. The register address pointer will overflow if the

initial register address is larger than zero. After the last

byte of data, the master does not acknowledge the

transfer but does generate a STOP condition.

8

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