FS6377-01I データシートの表示（PDF） - AMI Semiconductor
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FS6377-01I Datasheet PDF : 21 Pages
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FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Data Sheet
6.0 Programming Information
Table 3. Register Map
ADDRESS
BYTE 15
BYTE 14
BYTE 13
BYTE 12
BYTE 11
BYTE 10
BYTE 9
BYTE 8
BYTE 7
BYTE 6
BYTE 5
BYTE 4
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MUX_D2[1:0]
(selected via SEL_CD = 1)
MUX_C2[1:0]
(selected via SEL_CD = 1)
POST_D2[3:0]
(selected via SEL_CD = 1)
POST_D1[3:0]
(selected via SEL_CD = 0)
PDPOST_D PDPOST_C PDPOST_B PDPOST_A
POST_C2[3:0]
(selected via SEL_CD = 1)
POST_C1[3:0]
(selected via SEL_CD = 0)
POST_B[3:0]
POST_A[3:0]
MUX_D1[1:0]
(selected via SEL_CD = 0)
Reserved (0)
LFTC_C2
(SEL_CD=1)
CP_C2
(SEL_CD=1)
FBKDIV_C2[7:3] M-Counter
(selected via SEL_CD pin = 1)
REFDIV_C2[7:0]
(selected via SEL_CD pin = 1)
MUX_C1[1:0]
(selected via SEL_CD = 0)
PDPLL_C
LFTC_C1
CP_C1
(SEL_CD=0) (SEL_CD=0)
FBKDIV_C1[7:3] M-Counter
(selected via SEL_CD = 0)
REFDIV_C1[7:0]
(selected via SEL_CD = 0)
FBKDIV_D2[10:8] M-Counter
(selected via SEL_CD pin = 1)
FBKDIV_C2[2:0] A-Counter
(selected via SEL_CD pin = 1)
FBKDIV_C1[10:8] M-Counter
(selected via SEL_CD = 0)
FBKDIV_C1[2:0] A-Counter
(selected via SEL_CD = 1)
MUX_B[1:0]
PDPLL_B
LFTC_B
CP_B
FBKDIV_B[10:8] M-Counter
FBKDIV_B[7:3] M-Counter
FBKDIV_B[2:0] A-Counter
BYTE 3
REFDIV_B[7:0]
BYTE 2
MUX_A[1:0]
PDPLL_A
LFTC_A
CP_A
FBKDIV_A[10:8] M-Counter
BYTE 1
FBKDIV_A[7:3] M-Counter
FBKDIV_A[2:0] A-Counter
BYTE 0
(Note: All register bits are cleared to zero on power-up)
REFDIV_A[7:0]
6.1 Control Bit Assignment
If any PLL control bit is altered during device operation,
including those bits controlling the reference and feedback
dividers, the output frequency will slew smoothly (in a
glitch-free manner) to the new frequency. The slew rate is
related to the programmed loop filter time constant.
However, any programming changes to any mux or post
divider control bits will cause a glitch on an operating clock
output.
6.1.1 Power Down
All power-down functions are controlled by enable bits.
The bits select which portions of the device to power-down
when the PD input is asserted.
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