FS6370 データシートの表示（PDF） - ON Semiconductor
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FS6370 Datasheet PDF : 28 Pages
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FS6370
8.1.3. STOP Data Transfer
A low to high transition of the SDA line while SCL is held high indicates a STOP condition. All commands to the device must be
followed by a STOP condition.
8.1.4. Data Valid
The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL line after a START
condition occurs. The data on the SDA line must be changed only during the low period of the SCL signal. There is one clock pulse per
data bit.
Each data transfer is initiated by a START condition and terminated with a STOP condition. The number of data bytes transferred
between START and STOP conditions is determined by the master device, and can continue indefinitely. However, data that is
overwritten to the device after the first 16 bytes will overflow into the first register, then the second, and so on, in a first-in, first-
overwritten fashion.
8.1.5. Acknowledge
When addressed, the receiving device is required to generate an acknowledge after each byte is received. The master device must
generate an extra clock pulse to coincide with the acknowledge bit. The acknowledging device must pull the SDA line low during the
high period of the master acknowledge clock pulse. Setup and hold times must be taken into account.
The master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been read (clocked)
out of the slave. In this case, the slave must leave the SDA line high to enable the master to generate a STOP condition.
8.2 I2C-bus Operation
All programmable registers can be accessed randomly or sequentially via this bi-directional two wire digital interface. The device
accepts the following I2C-bus commands.
8.2.1. Device Address
After generating a START condition, the bus master broadcasts a seven-bit device address followed by a R/W bit.
The device address of the FS6370 is:
A6
A5
A4
A3
A2
A1
A0
1
0
1
1
1
0
0
Any one of eight possible addresses are available for the EEPROM. The least significant three bits are don’t care’s.
A6
A5
A4
A3
A2
A1
A0
1
0
1
0
X
X
X
8.2.2. Random Register Write Procedure
Random write operations allow the master to directly write to any register. To initiate a write procedure, the R/W bit that is transmitted
after the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the
slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an
acknowledge by the slave, the master is allowed to write eight bits of data into the addressed register. A final acknowledge is returned
by the device, and the master generates a STOP condition.
If either a STOP or a repeated START condition occurs during a register write, the data that has been transferred is ignored.
8.2.3. Random Register Read Procedure
Random read operations allow the master to directly read from any register. To perform a read procedure, the R/W bit that is
transmitted after the seven-bit address is a logic-low, as in the register write procedure. This indicates to the addressed slave device
that a register address will follow after the slave device acknowledges its device address. The register address is then written into the
slave's address pointer.
Rev. 3 | Page 9 of 28 | www.onsemi.com
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