GLT4116-45J4 データシートの表示（PDF） - G-Link Technology
部品番号
コンポーネント説明
メーカー
GLT4116-45J4 Datasheet PDF : 16 Pages
| |||
GLT41116
FUNCTIONAL BLOCK DIAGRAM
A[7:0]
VCC
GND
RAS
LCAS
UCAS
WE
OE
Column
Address Buffer
Y[7:0]
Row
Address Buffer
X[7:0]
CAS-before-RAS
Counter
Clock Generator
Column Decoder
••• 256 •••
x 16
Sense Amplifier
••• 256 x 16 •••
Memory Array
256 x 256 x 16
Lower Byte Control
Upper Byte Control
Data Output
x8
Buffer
x8
Data Input
x8
Buffer
x8
Data Output
x8
Buffer
x8
Data Input
x8
Buffer
x8
Figure 1. GLT41116 64 x 16 CMOS
DQ[7:0]
DQ[15:8]
Signal Descriptions
Symbol
A0 - A7
RAS
UCAS
LCAS
WE
OE
DQ[15:0]
VCC
VSS
NC
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Address Inputs
Row address strobe
Column address strobe/upper byte control
Column address strobe/lower byte control
Write enable
Output enable
Data inputs/outputs
+5V power supply
Ground
No connection
Description
2
G-LINK Technology
July 1998 (Rev. 1)
Share Link: 