GS816272C-133(2005) データシートの表示（PDF） - Giga Semiconductor

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GS816272C-133
(Rev.:2005)

256K x 72 18Mb Sync Burst SRAMs

Giga Semiconductor 

GS816272C

Undershoot Measurement and Timing

VIH

VSS

50%

VSS – 2.0 V

50% tKC

Overshoot Measurement and Timing

VDD + 2.0 V

50%

50% tKC

VDD

VIL

Capacitance

(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)

Parameter

Symbol

Input Capacitance

CIN

Input/Output Capacitance

CI/O

Note:

These parameters are sample tested.

Test conditions

VIN = 0 V

VOUT = 0 V

AC Test Conditions

Parameter

Conditions

Input high level

VDD – 0.2 V

Input low level

0.2 V

Input slew rate

1 V/ns

Input reference level

VDD/2

Output reference level

VDDQ/2

Output load

Fig. 1

Notes:

1. Include scope and jig capacitance.

2. Test conditions as specified with output loading as shown in Fig. 1

unless otherwise noted.

3. Device is deselected as defined by the Truth Table.

Typ. Max. Unit

4

5

pF

6

7

pF

Output Load 1

DQ

50Ω

30pF*

VDDQ/2

* Distributed Test Jig Capacitance

Rev: 2.18 11/2005

11/31

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 1999, GSI Technology

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