HB54A2568KN データシートの表示（PDF） - Elpida Memory, Inc
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HB54A2568KN Datasheet PDF : 16 Pages
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HB54A2568KN-A75B/B75B/10B
Block Diagram
/S1
/S0
DQS0
DM0
DQ0 to DQ7
DQS1
DM1
DQ8 to DQ15
RS
RS
8 RS
RS
RS
8 RS
LDQS /S
LDM
I/O0 to I/O7
UDQS D0
UDM
I/O8 to I/O15
LDQS /S
LDM
I/O0 to I/O7
UDQS D4
UDM
I/O8 to I/O15
DQS4
DM4
DQ32 to DQ39
DQS5
DM5
DQ40 to DQ47
RS
RS
8 RS
RS
RS
8 RS
LDQS /S
LDM
I/O0 to I/O7
UDQS D2
UDM
I/O8 to I/O15
LDQS /S
LDM
I/O0 to I/O7
UDQS D6
UDM
I/O8 to I/O15
DQS2
DM2
DQ16 to DQ23
DQS3
DM3
DQ24 to DQ31
RS
RS
8 RS
RS
RS
8 RS
LDQS /S
LDM
I/O0 to I/O7
UDQS D1
UDM
I/O8 to I/O15
LDQS /S
LDM
I/O0 to I/O7
UDQS D5
UDM
I/O8 to I/O15
DQS6
DM6
DQ48 to DQ55
DQS7
DM7
DQ56 to DQ63
RS
RS
8 RS
RS
RS
8 RS
LDQS /S
LDM
I/O0 to I/O7
UDQS D3
UDM
I/O8 to I/O15
LDQS /S
LDM
I/O0 to I/O7
UDQS D7
UDM
I/O8 to I/O15
BA0 to BA1
A0 to AN
/RAS
/CAS
/WE
CKE0
CKE1
VCCSPD
VREF
VCC
VSS
VCCID
Open
SDRAMs (D0 to D7)
SDRAMs (D0 to D7)
SDRAMs (D0 to D7)
SDRAMs (D0 to D7)
SDRAMs (D0 to D7)
SDRAMs (D0 to D3)
SDRAMs (D4 to D7)
SPD
SDRAMs (D0 to D7)
SDRAMs (D0 to D7), VCC and VCCQ
SDRAMs (D0 to D7), SPD
* D0 to D7 : 256M bits DDR SDRAM
U0 : 2k bits EEPROM
Rs : 22Ω
Serial PD
SCL
SCL
SDA
SDA
SA0
A0 U0
SA1
A1
SA2
A2 WP
CK0
/CK0
CK1
/CK1
4 loads
4 loads
CK2
/CK2
10 pF
Notes :
1. DQ wiring may differ from that described
in this drawing; however DQ/DM/DQS
relationships are maintained as shown.
VCCID strap connections:
(for memory device VCC, VCCQ)
Strap out (open): VCC = VCCQ
Strap in (closed): VCC ≠ VCCQ
2. The SDA pull-up registor is reguired due to
the open-drain/open-collector output.
3. The SCL pull-up registor is recommended,
because of the normal SCL lime inactive
"high" state.
Preliminary Data Sheet E0148H20 (Ver. 2.0)
9
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