HDD16M72D9RPW データシートの表示（PDF） - Hanbit Electronics Co.,Ltd
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HDD16M72D9RPW
Hanbit Electronics Co.,Ltd
HDD16M72D9RPW Datasheet PDF : 10 Pages
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HANBit
HDD16M72D9RPW
AC Timming Parameters & Specifications (These AC charicteristics were tested on the Component)
DDR200
DDR266A
DDR266B
PARAMETER
SYMBOL
-10A
-13A
-13B
UNIT NOTE
MIN MAX MIN MAX MIN MAX
Row cycle time
Refresh row cycle time
Row active time
/RAS to /CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. address to Col. address delay
Clock cycle time
CL=2.0
CL=2.5
tRC
tRFC
tRAS
tRCD
tRP
tRRD
tWR
tCDLR
tCCD
tCK
70
65
65
ns
1
80
75
75
ns 1,2
48 120K 45
120K 45 120K ns 1,2
20
20
20
ns
3
20
20
20
ns
3
15
15
15
ns
3
2
2
2
tCK
3
1
1
1
tCK
2
1
1
1
tCK
10
12
7.5
12
10
12
ns
12
7.5
12
7.5
12
ns
Clock high level width
tCH
0.45 0.55 0.45 0.55 0.45 0.55 tCK
Clock low level width
tCL
0.45 0.55 0.45 0.55 0.45 0.55 tCK
DQS-out access time from CK/CK
tDQSCK -0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns
Output data access time from CK/CK
tAC
-0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns
Data strobe edge to ouput data edge
tDQSQ
-
+0.6
-
+0.5
-
+0.5 ns
Read Preamble
tRPRE
0.9 1.1
0.9
1.1
0.9
1.1
tCK
Read Postamble
tRPST
0.4 0.6
0.4
0.6
0.4
0.6
tCK
Data out high impedence time from CK-/CK tHZQ
-0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns
2
CK to valid DQS-in
tDQSS
0.75 1.25 0.75
1.25 0.75 1.25
tCK
DQS-in setup time
tWPRES
0
0
0
ns
3
DQS-in hold time
tWPREH
0.25
0.25
0.25
tCK
DQS-in falling edge to CK rising-setup time tDSS
0.2
0.2
0.2
tCK
DQS-in falling edge to CK rising hold time
tDSH
0.2
0.2
0.2
tCK
DQS-in high level width
tDQSH
0.35
0.35
0.35
tCK
DQS-in low level width
tDQSL
0.35
0.35
0.35
tCK
DQS-in cycle time
tDSC
0.9 1.1
0.9
1.1
0.9
1.1
tCK
Address and Control Input setup time
tIS
1.1
0.9
0.9
ns
Address and Control Input hold time
tIH
1.1
0.9
0.9
ns
Mode register set cycle time
tMRD
16
15
15
ns
DQ & DM setup time to DQS
tDS
0.6
0.5
0.5
ns
DQ & DM hold time to DQS
tDH
0.6
0.5
0.5
ns
DQ & DM input pulse width
tDIPW
2
1.75
1.75
ns
Power down exit time
tPDEX
10
10
10
ns
Exit self refresh to write command
tXSW
116
95
ns
Exit self refresh to bank active command
tXSA
80
75
75
ns
Exit self refresh to read command
tXSR
200
200
200
Cycle
Refresh interval time
tREF
15.6
15.6
15.6
us
1
Output DQS valid window
tQH
0.35
0.35
0.35
tCK
DQS write postamble time
tWPST
0.25
0.25
0.25
tCK
4
URL : www.hbe.co.kr
REV 1.0 (November.2002)
7
HANBit Electronics Co.,Ltd.
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