HI-8281 データシートの表示（PDF） - Holt Integrated Circuits

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HI-8281

ARINC 429 LINE DRIVER AND DUAL RECEIVER

Holt Integrated Circuits 

HI-8281

FUNCTIONAL DESCRIPTION (cont.)

LINE DRIVER OPERATION

The line driver in the HI-8281 is designed to directly drive the

ARINC 429 bus. The two ARINC outputs (TXA(OUT) and

TXB(OUT)) provide a differential voltage to produce a +10 volt

One, a -10 volt Zero, and a 0 volt Null. The device incorporates on

board zeners to translate internal CMOS levels to ARINC specified

amplitudes. A logic input (SLP1.5) is provided to control the slope

of the differential output signal. No additional hardware is required

to control the slope. A HIGH on SLP1.5 causes a slope of 1.5 µs on

the ARINC outputs. A LOW on SLP1.5 causes a slope of 10 µs.

Timing is set by on-chip resistor and capacitor and tested to be

within ARINC requirements. The HI-8281 has 37.5 ohms in series

with each line driver output.

REPEATER OPERATION

Repeater mode of operation allows a data word that has been

received by the HI-8281 to be placed directly into its FIFO for

transmission. Repeater operation is similar to normal receiver

operation. In normal operation, either byte of a received data word

may be read from the receiver latches first by use of SEL input.

During repeater operation however, the lower byte of the data word

must be read first. This is necessary because, as the data is being

read, it is also being loaded into the FIFO and the transmitter FIFO

is always loaded with the lower byte of the data word first. Signal

flow for repeater operation is shown in the Timing Diagrams

section.

TIMING DIAGRAMS

DATA RATE - EXAMPLE PATTERN

TXA(OUT)

TXB(OUT)

ARINC BIT

DATA

NULL

BIT 30

DATA

NULL

BIT 31

DATA

NULL

BIT 32

WORD GAP

BIT 1

NEXT WORD

LOADING CONTROL WORD

DATA BUS

CWSTR

VALID

tCWSET

tCWHLD

tCWSTR

ARINC DATA

BIT 31

DATA READY FLAG D/R

BYTE SELECT SEL

ENABLE BYTE ON BUS EN

DATA BUS

BIT 32

RECEIVER OPERATON

tD/R

DON'T CARE

tSELEN

tD/REN

tENDATA

tENSEL

DON'T CARE

tEND/R

tEN

tSELEN

DON'T CARE

tENSEL

BYTE 1 VALID

tENEN

tDATAEN

tENDATA

BYTE 2 VALID

tDATAEN

HOLT INTEGRATED CIRCUITS

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