HM64YLB36514 データシートの表示（PDF） - Renesas Electronics

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HM64YLB36514

16M Synchronous Late Write Fast Static RAM (512-kword × 36-bit, Register-Latch Mode)

Renesas Electronics 

HM64YLB36514 Series

Programmable Impedance Output Drivers

Output buffer impedance can be programmed by terminating the ZQ pin to VSS through a precision resistor

(RQ). The value of RQ is five times the output impedance desired. The allowable value of RQ to

guarantee impedance matching with a tolerance of 15% is 250 Ω. If the status of ZQ pin is open, output

impedance is maximum value. Maximum impedance also occurs with ZQ connected to VDDQ. The

impedance update of the output driver occurs when the SRAM is in high-Z. Write and deselect operations

will synchronously switch the SRAM into and out of high-Z, therefore will trigger an update. The user

may choose to invoke asynchronous G updates by providing a G setup and hold about the K clock, to

guarantee the proper update. At power up, the output buffer is in high-Z. It will take 4,096 cycles for the

impedance to be completely updated.

Rev.0.10, May.15.2003, page 6 of 22

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