HMS30C7202N データシートの表示（PDF） - MagnaChip Semiconductor

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HMS30C7202N

Highly-intergrated MPU

MagnaChip Semiconductor 

HMS30C7202N

There are two APB buses, the fast and slow APB bus. The fast APB bus operates at the speed of the ASB,

and hosts the USB interface, the sound output interface, the LCD registers, etc. These are the high

performance peripherals, which are generally DMA targets. The slow APB peripherals generally operate at the

UART crystal clock frequency of 3.6864MHz, though register access via the APB is at ASB speed.

The slow APB peripherals do not support DMA transfers. This arrangement of running most of the peripherals

at a slower clock, and reducing the load on the faster bus, results in significantly reduced power consumption.

Both APB buses connect to the main ASB bus via bridges. The slow APB bridge takes care of all

resynchronization, handing over data and control signals between the ASB and UART clock domains in a safe

and reliable manner.

The fast APB Bridge is modified from the normal AMBA Bridge, to allow DMA access to fast APB peripherals.

Additional signals from the DMA controller to the APB bridge request select and acknowledge DMA transfers

to and from DMA-aware peripherals.

1.5 SDRAM Controller

The SDRAM controller is a key part of the HMS30C7202 architecture. The SDRAM controller has two data

ports - one for video DMA and one for the main ASB - and interfaces to 16-bit wide SDRAMs. One to four 16,

64, 128, or 256 Mbit x16-bit devices are supported, giving a memory size ranging from 2 to 64 Mbytes.

The main ASB and video DMA buses are independent, and operate concurrently. The video bus has always

higher priority than the main bus.

The video interface consists of address, data and control signals. The video access burst size is fixed to 16

words. The address is non-incrementing for words within a burst (as the SDRAM controller only makes use of

the first address for each burst request).

1.6 Peripheral DMA

1.6.1 Overview

HMS30C7202 incorporates a four-channel, general-purpose DMA controller that operates on the ASB. The

DMA controller is an AMBA compliant ASB bus master with a higher arbitration priority than the ARM

processor, to ensure low DMA latency. Since, however, the main ASB bus always has lower priority access to

the SDRAM controller than the video bus, it will always get lower priority access to SDRAM than the LCD.

1.6.2 Transfer sizes

A device that uses the peripheral DMA is the Sound output. The sound output data rate is 88.2KB/sec. To

ensure reasonable usage of SDRAM, APB and ASB bandwidth, the transfer sizes to the sound controller is a

single word.

The SDRAM controller does a complete quad-word access for every SDRAM access. The maximum SDRAM

bandwidth taken by sound device running concurrently is 0.75%.

DMA accesses to Sound blocks are fully AMBA compliant, meaning that a word transfer takes two bus cycles.

1.6.3 Fly-by

The DMA controller is tightly coupled to the fast APB Bridge. In order for the DMA Controller to start a transfer,

it must first receive a DMA data request from one of the peripherals; it will then request mastership of the ASB.

Once granted, the DMA Controller will retain mastership of the ASB until the requested DMA transaction is

completed, which ensures correct data in the DMA peripherals (i.e. the ARM core cannot modify data while a

DMA transfer is in progress).

The DMA transfer request is monitored by the Fast APB bridge, which performs the correspondent APB

transfer by inverting the read/write line with respect to the ASB and generates a PWRITE signal on the APB.

The DMA transfer is acknowledged on the APB by asserting a PSELDMA signal for the given peripheral. The

data is timed by PSTB as on a normal APB transfer. The APB address PA is not used for DMA transfers.

The APB bridge receives two signals from the DMA controller called CHAN [1:0], which tells it which DMA

channel (peripheral) the DMA access is for. All other information comes from monitoring the ASB bus signals.

For example, the direction of transfer comes from BWRITE (the sense is inverted to get the APB signal), and

© 2004 MagnaChip Semiconductor Ltd. All Ri1g0hts Reserved.

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