HMS30C7202N データシートの表示（PDF） - MagnaChip Semiconductor

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HMS30C7202N

Highly-intergrated MPU

MagnaChip Semiconductor 

HMS30C7202N

peripherals to be clocked slowly hence reducing power consumption. The use of three buses reduces the

number of nodes that are toggled during a data access, and thereby further reducing power consumption. In

addition, clocks to peripherals that are not active can also be gated.

1.8.1 Clock gating

The high performance peripherals, such as the SDRAM controller and the LCD controller, run most of the time

at high frequencies and careful design, including the use of clock gating, has minimized their power

consumption. Any peripherals can be powered down completely when not in use.

1.8.2 PMU

The Power Management Unit (PMU) is used to control the overall state the system is in. The system can be in

one of five states:

Run

The system is running normally. All clocks are running (except where gated locally), and the SDRAM controller is

performing normal refresh.

Slow

The system operates normally, except the ARM is placed into Fast Bus mode, and hence is clocked at half its normal

rate.

Idle

In this mode, the PMU becomes the bus master until there is an interrupt for the CPU, or the peripheral DMA controller

requests mastership of the bus.

Sleep

The SDRAM is placed into self-refresh mode, and internal clocks are gated off. This mode can only be entered from

Idle mode (that is, the PMU must be ASB master before this mode can be entered). The PMU must get bus mastership

to ensure that the system is stopped in a safe state and not, for example, halfway through an SDRAM write. Usually

this state is only to be entered briefly, on the way to entering deep sleep mode.

Deep Sleep

In deep sleep mode, the 3.6864MHz oscillator and the PLLs are disabled. This is the lowest power state available.

Only the 32kHz oscillator runs. The real time clock and wakeup sections of the PMU are operated from this clock.

Everything else is powered down, and SDRAM is in self-refresh mode. This is the normal system “off” mode. Sleep and

Deep Sleep modes are exited either by a user wake-up event (generally pressing the “On” key), an RTC wake-up

alarm, a device reset request, or by a modem ring indicate event. These interrupt sources go directly to the PMU. In

addition, the modem ring indicate signal also goes to the normal interrupt controller to signal an interrupt if there is a

ring indicate event in a non-sleep mode.

1.9 Test and debug

The HMS30C7202 incorporates the ARM standard test interface controller (TIC) allowing 32-bit parallel test

vectors to be passed onto the internal bus. This allows access to the ARM720T macro-cell core, and also to

memory mapped devices and peripherals within the HMS30C7202. In addition, the ARM720T includes

support for the ARM debug architecture (Embedded ICE), which makes use of a JTAG boundary scan port to

support debug of code on the embedded processor. The same boundary scan port is also used to support a

normal pad-ring boundary scan for board level test applications.]

© 2004 MagnaChip Semiconductor Ltd. All Ri1g2hts Reserved.

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