HYB5117405BT-700 データシートの表示（PDF） - Siemens AG

部品番号

コンポーネント説明

メーカー

HYB5117405BT-700

4M x 4-Bit Dynamic RAM 2k & 4k Refresh (Hyper Page Mode- EDO)

Siemens AG 

4M x 4-Bit Dynamic RAM

2k & 4k Refresh

(Hyper Page Mode- EDO)

Advanced Information

HYB5116405BJ/BT -50/-60/-70

HYB5117405BJ/BT -50/-60/-70

• 4 194 304 words by 4-bit organization

• 0 to 70 °C operating temperature

• Performance:

tRAC

tCAC

tAA

tRC

tHPC

RAS access time

CAS access time

Access time from address

Read/Write cycle time

Hyper page mode (EDO)

cycle time

-50 -60 -70

50 60 70 ns

13 15 20 ns

25 30 35 ns

84 104 124 ns

20 25 30 ns

• Single + 5 V (± 10 %) supply

• Low power dissipation

max. 550 mW active (HYB5116405BJ/BT-50)

max. 495 mW active (HYB5116405BJ/BT-60)

max. 440 mW active (HYB5116405BJ/BT-70)

max. 660 mW active (HYB5117405BJ/BT-50)

max. 605 mW active (HYB5117405BJ/BT-60)

max. 550 mW active (HYB5117405BJ/BT-70)

11 mW standby (TTL)

5.5. mW standby (MOS)

• Output unlatched at cycle end allows two-dimensional chip selection

• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,

self refresh and test mode

• Hyper page mode (EDO) capability

• All inputs, outputs and clocks fully TTL-compatible

• 4096 refresh cycles / 64 ms for HYB5116405BJ/BT (4k-Refresh)

• 2048 refresh cycles / 32 ms for HYB5117405BJ/BT (2k-Refresh)

• Plastic Package:

P-SOJ-26/24 300 mil

P TSOPII-26/24 300 mil

Semiconductor Group

1

1.96

Share Link: