HYB5116405BJ-60 データシートの表示（PDF） - Siemens AG

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HYB5116405BJ-60

4M x 4-Bit Dynamic RAM 2k & 4k Refresh (Hyper Page Mode- EDO)

Siemens AG 

HYB5116(7)405BJ/BT-50/-60/-70

4M x 4-EDO DRAM

AC Characteristics 5)6)

16E

TA = 0 to 70 °C,VCC = 5 V ± 10 %, tT = 2 ns

Parameter

Symbol

Limit Values

Unit Note

-50

-60

-70

min. max. min. max. min. max.

common parameters

Random read or write cycle time tRC

RAS precharge time

tRP

RAS pulse width

tRAS

CAS pulse width

tCAS

Row address setup time

tASR

Row address hold time

tRAH

Column address setup time

tASC

Column address hold time

tCAH

RAS to CAS delay time

tRCD

RAS to column address delay

tRAD

RAS hold time

tRSH

CAS hold time

tCSH

CAS to RAS precharge time

tCRP

Transition time (rise and fall)

tT

Refresh period for HYB5116405 tREF

Refresh period for HYB5117405 tREF

84 –

104 –

124 –

ns

30 –

40 –

50 –

ns

50 10k 60 10k 70 10k ns

8

10k 10 10k 12 10k ns

0

–

0

–

0

–

ns

8

–

10 –

10 –

ns

0

–

0

–

0

–

ns

8

–

10 –

12 –

ns

12 37 14 45 14 53 ns

10 25 12 30 12 35 ns

13

15 –

17 –

ns

40

50 –

60 –

ns

5

–

5

–

5

–

ns

1

50 1

50 1

50 ns 7

–

64 –

64 –

64 ms

–

32 –

32 –

32 ms

Read Cycle

Access time from RAS

tRAC

Access time from CAS

tCAC

Access time from column address tAA

OE access time

tOEA

Column address to RAS lead time tRAL

Read command setup time

tRCS

Read command hold time

tRCH

Read command hold time

tRRH

referenced to RAS

CAS to output in low-Z

tCLZ

Output buffer turn-off delay

tOFF

–

50 –

60 –

70 ns 8, 9

–

13 –

15 –

17 ns 8, 9

–

25 –

30 –

35 ns 8,10

–

13 –

15 –

17 ns

25 –

30 –

35 –

ns

0

–

0

–

0

–

ns

0

–

0

–

0

–

ns 11

0

–

0

–

0

–

ns 11

0

–

0

–

0

–

ns 8

0

13 0

15 0

17 ns 12

Semiconductor Group

8

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