IDT54FCT841CLB データシートの表示（PDF） - Integrated Device Technology
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IDT54FCT841CLB Datasheet PDF : 7 Pages
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IDT54/74FCT841A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCHES
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
VCC
7.0V
VIN
Pulse
Generator
D.U.T.
RT
VOUT
50pF
CL
500Ω
500Ω
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Enable Low
Closed
All Other Tests
Open
DEFINITIONS:
2607 tbl 08
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA
INPUT
TIMING
tSU
tH
3V
1.5V
0V
3V
LOW-HIGH-LOW
PULSE
INPUT
1.5V
ASYNCHRONOUS CONTROL
PRESET
tREM
0V
3V
tW
CLEAR
ETC.
1.5V
0V
HIGH-LOW-HIGH
PULSE
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
tSU
tH
3V
1.5V
0V
ETC.
1.5V
1.5V
PROPAGATION DELAY
SAME PHASE
INPUT TRANSITION
tPLH
tPHL
OUTPUT
tPLH
tPHL
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
VOH
1.5V
VOL
3V
1.5V
0V
ENABLE AND DISABLE TIMES
ENABLE
DISABLE
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
tPZL
SWITCH
CLOSED
tPZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
tPLZ
3.5V
1.5V
tPHZ
1.5V
0V
3V
1.5V
0V
3.5V
0.3V VOL
0.3V VOH
0V
NOTES:
2607 drw 04
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
7.22
6
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