IDT6167SA100D データシートの表示（PDF） - Integrated Device Technology

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IDT6167SA100D

CMOS STATIC RAM 16K (16K x 1-BIT)

Integrated Device Technology 

IDT6167SA/LA

CMOS STATIC RAM 16K (16K x 1-BIT)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1, (WE CONTROLLED TIMING)(1, 2, 4)

tWC

ADDRESS

tAW

CS

tAS

tWP

(3)

tWR

tCHZ (5)

WE

DATAOUT

DATAIN

tWHZ (5)

(6)

PREVIOUS DATAOUT VALID

tOW (5)

tDW

tDH

DATAIN VALID

DATAOUT

VALID (6)

2981 drw 08

TIMING WAVEFORM OF WRITE CYCLE NO. 2, (CS CONTROLLED TIMING)(1, 2, 4)

tWC

ADDRESS

CS

tAS

WE

tAW

tCW

tWR (3)

tDW

tDH

DATAIN

DATAIN VALID

NOTES:

1. WE or CS must be inactive during all address transitions.

2. A write occurs during the overlap of a LOW CS and a LOW WE.

3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.

4. If the CS low transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.

5. Transition is measured ±200mV from steady state.

6. During this period, the I/O pins are in the output state and the input signals must not be applied.

2981 drw 09

5.2

7

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