62256 データシートの表示（PDF） - Samsung

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62256

32Kx8 bit Low Power CMOS Static RAM

Samsung 

KM62256C Family

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE (1()Address Controlled)

( CS=OE=VIL, WE=VIH)

Address

Data Out

tRC

tAA

tOH

Previous Data Valid

PRELIMINARY

CMOS SRAM

Data Valid

TIMING WAVEFORM OF READ CYCLE(2()WE=VIH)

Address

CS

OE

Data out

High-Z

tRC

tAA

tCO

tOE

tOLZ

tLZ

tOH

tHZ

tOHZ

Data Valid

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.

2. At any given temperature and voltage condition, tHZ(max.) is less than tLZ(min.) both for a given device and from device to device.

Revision 3.0

April 1996

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